IEEE International Test Conference, ITC 2016


Title/Authors Title Research Artifacts
[?] A research artifact is any by-product of a research project that is not directly included in the published research paper. In Computer Science research this is often source code and data sets, but it could also be media, documentation, inputs to proof assistants, shell-scripts to run experiments, etc.
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Test point insertion in hybrid test compression/LBIST architectures

Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada

Test point insertion in hybrid test compression/LBIST architectures

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Keynote address Wednesday: Hardware inference accelerators for machine learning

Rob A. Rutenbar

Keynote address Wednesday: Hardware inference accelerators for machine learning

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Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board

Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada

Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board

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Mixed-signal ATE technology and its impact on today's electronic system

Gordon W. Roberts

Mixed-signal ATE technology and its impact on today's electronic system

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Transformation of multiple fault models to a unified model for ATPG efficiency enhancement

Cheng-Hung Wu, Kuen-Jong Lee

Transformation of multiple fault models to a unified model for ATPG efficiency enhancement

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Supply-voltage optimization to account for process variations in high-volume manufacturing testing

Gurunath Kadam, Markus Rudack, Krishnendu Chakrabarty, Juergen Alt

Supply-voltage optimization to account for process variations in high-volume manufacturing testing

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Test chip design for optimal cell-aware diagnosability

Soumya Mittal, Zeye Dexter Liu, Ben Niewenhuis, R. D. (Shawn) Blanton

Test chip design for optimal cell-aware diagnosability

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An on-chip self-test architecture with test patterns recorded in scan chains

Kuen-Jong Lee, Pin-Hao Tang, Michael A. Kochte

An on-chip self-test architecture with test patterns recorded in scan chains

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Active reliability monitor: Defect level extrinsic reliability monitoring on 22nm POWER8 and zSeries processors

Michael Johnson, Brian Noble, Mark Johnson, Jim Crafts, Cynthia Manya, John Deforge

Active reliability monitor: Defect level extrinsic reliability monitoring on 22nm POWER8 and zSeries processors

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Accurate anomaly detection using correlation-based time-series analysis in a core router system

Shi Jin, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu

Accurate anomaly detection using correlation-based time-series analysis in a core router system

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BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning

Mehdi Sadi, Gustavo K. Contreras, Dat Tran, Jifeng Chen, LeRoy Winemberg, Mark Tehranipoor

BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning

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Automatic test signal generation for mixed-signal integrated circuits using circuit partitioning and interval analysis

Anthony Coyette, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen

Automatic test signal generation for mixed-signal integrated circuits using circuit partitioning and interval analysis

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Output bit selection methodology for test response compaction

Wei-Cheng Lien, Kuen-Jong Lee

Output bit selection methodology for test response compaction

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RF test accuracy and capacity enhancement on ATE for silicon TV tuners

Y. Fan, A. Verma, Y. Su, L. Rose, J. Janney, V. Do, S. Kumar

RF test accuracy and capacity enhancement on ATE for silicon TV tuners

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Accessing 1687 systems using arbitrary protocols

Michele Portolan

Accessing 1687 systems using arbitrary protocols

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Using symbolic canceling to improve diagnosis from compacted response

Kamran Saleem, Nur A. Touba

Using symbolic canceling to improve diagnosis from compacted response

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A built-in self-repair scheme for DRAMs with spare rows, columns, and bits

Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou

A built-in self-repair scheme for DRAMs with spare rows, columns, and bits

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Diagnostic resolution improvement through learning-guided physical failure analysis

Carlston Lim, Yang Xue, Xin Li, Ronald D. Blanton, M. Enamul Amyeen

Diagnostic resolution improvement through learning-guided physical failure analysis

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Built-in self-test for micro-electrode-dot-array digital microfluidic biochips

Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee

Built-in self-test for micro-electrode-dot-array digital microfluidic biochips

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Handling wrong mapping: A new direction towards better diagnosis with low pin convolution compressors

Subhadip Kundu, Parthajit Bhattacharya, Rohit Kapur

Handling wrong mapping: A new direction towards better diagnosis with low pin convolution compressors

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Securing digital microfluidic biochips by randomizing checkpoints

Jack Tang, Ramesh Karri, Mohamed Ibrahim, Krishnendu Chakrabarty

Securing digital microfluidic biochips by randomizing checkpoints

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A unified test and fault-tolerant multicast solution for network-on-chip designs

Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara

A unified test and fault-tolerant multicast solution for network-on-chip designs

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What we know after twelve years developing and deploying test data analytics solutions

Kenneth M. Butler, Amit Nahar, W. Robert Daasch

What we know after twelve years developing and deploying test data analytics solutions

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A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapath

V. R. Devanathan, Sumant Kale

A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapath

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Pylon: Towards an integrated customizable volume diagnosis infrastructure

Yan Pan, Rao Desineni, Kannan Sekar, Atul Chittora, Sherwin Fernandes, Neerja Bawaskar, John M. Carulli

Pylon: Towards an integrated customizable volume diagnosis infrastructure

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Keynote address Thursday: Addressing semiconductor industry needs: Defining the future through creative, exciting research

Ken Hansen

Keynote address Thursday: Addressing semiconductor industry needs: Defining the future through creative, exciting research

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Automated measurement of defect tolerance in mixed-signal ICs

Stephen Sunter, Alessandro Valerio, Riccardo Miglierina

Automated measurement of defect tolerance in mixed-signal ICs

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Variation and failure characterization through pattern classification of test data from multiple test stages

Chun-Kai Hsu, Peter Sarson, Gregor Schatzberger, Friedrich Peter Leisenberger, John M. Carulli Jr., Siddhartha Siddhartha, Kwang-Ting Cheng

Variation and failure characterization through pattern classification of test data from multiple test stages

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Harnessing process variations for optimizing wafer-level probe-test flow

Ali Ahmadi, Constantinos Xanthopoulos, Amit Nahar, Bob Orr, Michael Pas, Yiorgos Makris

Harnessing process variations for optimizing wafer-level probe-test flow

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Logic characterization vehicle design reflection via layout rewiring

Phillip Fynan, Zeye Dexter Liu, Benjamin Niewenhuis, Soumya Mittal, Marcin Strajwas, R. D. (Shawn) Blanton

Logic characterization vehicle design reflection via layout rewiring

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Upper-bound computation for optimal retargeting in IEEE1687 networks

Farrokh Ghani Zadegan, Rene Krenz-Baath, Erik Larsson

Upper-bound computation for optimal retargeting in IEEE1687 networks

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Known-good-die test methods for large, thin, high-power digital devices

Dave Armstrong, Gary Maier

Known-good-die test methods for large, thin, high-power digital devices

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Analog fault coverage improvement using final-test dynamic part average testing

Wim Dobbelaere, Ronny Vanhooren, Willy De Man, Koen Matthijs, Anthony Coyette, Baris Esen, Georges G. E. Gielen

Analog fault coverage improvement using final-test dynamic part average testing

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I-Q signal generation techniques for communication IC testing and ATE systems

Masahiro Murakami, Haruo Kobayashi, Shaiful Nizam Bin Mohyar, Osamu Kobayashi, Takahiro Miki, Junya Kojima

I-Q signal generation techniques for communication IC testing and ATE systems

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Efficient cross-layer concurrent error detection in nonlinear control systems using mapped predictive check states

Suvadeep Banerjee, Abhijit Chatterjee, Jacob A. Abraham

Efficient cross-layer concurrent error detection in nonlinear control systems using mapped predictive check states

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Machine learning-based defense against process-aware attacks on Industrial Control Systems

Anastasis Keliris, Hossein Salehghaffari, Brian R. Cairl, Prashanth Krishnamurthy, Michail Maniatakos, Farshad Khorrami

Machine learning-based defense against process-aware attacks on Industrial Control Systems

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EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays

Insik Yoon, Ashwin Chintaluri, Arijit Raychowdhury

EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays

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Testing of interposer-based 2.5D integrated circuits

Ran Wang, Krishnendu Chakrabarty

Testing of interposer-based 2.5D integrated circuits

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Advanced test methodology for complex SoCs

Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Ayub Abdollahian

Advanced test methodology for complex SoCs

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Effective DC fault models and testing approach for open defects in analog circuits

Baris Esen, Anthony Coyette, Georges G. E. Gielen, Wim Dobbelaere, Ronny Vanhooren

Effective DC fault models and testing approach for open defects in analog circuits

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A novel diagnostic test generation methodology and its application in production failure isolation

M. Enamul Amyeen, Dongok Kim, Maheshwar Chandrasekar, Mohammad Noman, Srikanth Venkataraman, Anurag Jain, Neha Goel, Ramesh Sharma

A novel diagnostic test generation methodology and its application in production failure isolation

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DE-LOC: Design validation and debugging under limited observation and control, pre- and post-silicon for mixed-signal systems

Barry John Muldrey, Sabyasachi Deyati, Abhijit Chatterjee

DE-LOC: Design validation and debugging under limited observation and control, pre- and post-silicon for mixed-signal systems

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Statistical outlier screening as a test solution health monitor

David Shaw, Dirk Hoops, Kenneth M. Butler, Amit Nahar

Statistical outlier screening as a test solution health monitor

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Fault simulation for analog test coverage

Jyotsna Sequeira, Suriyaprakash Natarajan, Prashant Goteti, Nitin Chaudhary

Fault simulation for analog test coverage

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SERDES external loopback test using production parametric-test hardware

Shalini Arora, Aman Aflaki, Sounil Biswas, Masashi Shimanouchi

SERDES external loopback test using production parametric-test hardware

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Online slack-time binning for IO-registered die-to-die interconnects

Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng

Online slack-time binning for IO-registered die-to-die interconnects

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Plenary keynote address Tuesday: The business of test: Test and semiconductor economics

Walden C. Rhines

Plenary keynote address Tuesday: The business of test: Test and semiconductor economics

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An accurate algorithm for computing mutation coverage in model checking

Huina Chao, Huawei Li, Tiancheng Wang, Xiaowei Li, Bo Liu

An accurate algorithm for computing mutation coverage in model checking

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Low cost ultra-pure sine wave generation with self calibration

Yuming Zhuang, Akhilesh Kesavan Unnithan, Arun Joseph, Siva Sudani, Benjamin Magstadt, Degang Chen

Low cost ultra-pure sine wave generation with self calibration

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Recycled FPGA detection using exhaustive LUT path delay characterization

Md Mahbub Alam, Mark Tehranipoor, Domenic Forte

Recycled FPGA detection using exhaustive LUT path delay characterization

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Minimal area test points for deterministic patterns

Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer

Minimal area test points for deterministic patterns

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A suite of IEEE 1687 benchmark networks

Anton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath

A suite of IEEE 1687 benchmark networks

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Putting wasted clock cycles to use: Enhancing fortuitous cell-aware fault detection with scan shift capture

Fanchen Zhang, Daphne Hwong, Yi Sun, Allison Garcia, Soha Alhelaly, Geoff Shofner, LeRoy Winemberg, Jennifer Dworak

Putting wasted clock cycles to use: Enhancing fortuitous cell-aware fault detection with scan shift capture

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Defect tolerance for CNFET-based SRAMs

Tianjian Li, Li Jiang, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty

Defect tolerance for CNFET-based SRAMs

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Novel crosstalk evaluation method for high-density signal traces using clock waveform conversion technique

Takayuki Nakamura, Koji Asami

Novel crosstalk evaluation method for high-density signal traces using clock waveform conversion technique

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Memory repair for high fault rates

Panagiota Papavramidou

Memory repair for high fault rates

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Cross-layer system reliability assessment framework for hardware faults

Alessandro Vallero, Alessandro Savino, Gianfranco Politano, Stefano Di Carlo, Athanasios Chatzidimitriou, Sotiris Tselonis, Manolis Kaliorakis, Dimitris Gizopoulos, Marc Riera, Ramon Canal, Antonio González, Maha Kooli, Alberto Bosio, Giorgio Di Natale

Cross-layer system reliability assessment framework for hardware faults

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Test time efficient group delay filter characterization technique using a discrete chirped excitation signal

Peter Sarson

Test time efficient group delay filter characterization technique using a discrete chirped excitation signal

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