| Title/Authors | Title | Research Artifacts
[?] A research
artifact is any by-product of a research project that is not
directly included in the published research paper. In Computer
Science research this is often source code and data sets, but
it could also be media, documentation, inputs to proof
assistants, shell-scripts to run experiments, etc.
|
Details |
|---|
|
Test point insertion in hybrid test compression/LBIST architectures Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada |
Test point insertion in hybrid test compression/LBIST architectures Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Keynote address Wednesday: Hardware inference accelerators for machine learning Rob A. Rutenbar |
Keynote address Wednesday: Hardware inference accelerators for machine learning Details |
|
Discussion Comments:
0
Verification:
Author has
not verified
information
|
|
Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Mixed-signal ATE technology and its impact on today's electronic system Gordon W. Roberts |
Mixed-signal ATE technology and its impact on today's electronic system Details |
|
Discussion Comments:
0
Verification:
Author has
not verified
information
|
|
Transformation of multiple fault models to a unified model for ATPG efficiency enhancement Cheng-Hung Wu, Kuen-Jong Lee |
Transformation of multiple fault models to a unified model for ATPG efficiency enhancement Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Supply-voltage optimization to account for process variations in high-volume manufacturing testing Gurunath Kadam, Markus Rudack, Krishnendu Chakrabarty, Juergen Alt |
Supply-voltage optimization to account for process variations in high-volume manufacturing testing Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Test chip design for optimal cell-aware diagnosability Soumya Mittal, Zeye Liu, Ben Niewenhuis, R. D. (Shawn) Blanton |
Test chip design for optimal cell-aware diagnosability Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
An on-chip self-test architecture with test patterns recorded in scan chains Kuen-Jong Lee, Pin-Hao Tang, Michael A. Kochte |
An on-chip self-test architecture with test patterns recorded in scan chains Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Michael Johnson, Brian Noble, Mark Johnson, Jim Crafts, Cynthia Manya, John Deforge |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Accurate anomaly detection using correlation-based time-series analysis in a core router system Shi Jin, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu |
Accurate anomaly detection using correlation-based time-series analysis in a core router system Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Mehdi Sadi, Gustavo K. Contreras, Dat Tran, Jifeng Chen, LeRoy Winemberg, Mark Tehranipoor |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Anthony Coyette, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Output bit selection methodology for test response compaction Wei-Cheng Lien, Kuen-Jong Lee |
Output bit selection methodology for test response compaction Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
RF test accuracy and capacity enhancement on ATE for silicon TV tuners Y. Fan, A. Verma, Y. Su, L. Rose, J. Janney, V. Do, S. Kumar |
RF test accuracy and capacity enhancement on ATE for silicon TV tuners Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Accessing 1687 systems using arbitrary protocols Michele Portolan |
Accessing 1687 systems using arbitrary protocols Details |
|
Discussion Comments:
0
Verification:
Author has
not verified
information
|
|
Using symbolic canceling to improve diagnosis from compacted response Kamran Saleem, Nur A. Touba |
Using symbolic canceling to improve diagnosis from compacted response Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou |
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Diagnostic resolution improvement through learning-guided physical failure analysis Carlston Lim, Yang Xue, Xin Li, Ronald D. Blanton, M. Enamul Amyeen |
Diagnostic resolution improvement through learning-guided physical failure analysis Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Built-in self-test for micro-electrode-dot-array digital microfluidic biochips Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee |
Built-in self-test for micro-electrode-dot-array digital microfluidic biochips Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Subhadip Kundu, Parthajit Bhattacharya, Rohit Kapur |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Securing digital microfluidic biochips by randomizing checkpoints Jack Tang, Ramesh Karri, Mohamed Ibrahim, Krishnendu Chakrabarty |
Securing digital microfluidic biochips by randomizing checkpoints Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
A unified test and fault-tolerant multicast solution for network-on-chip designs Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara |
A unified test and fault-tolerant multicast solution for network-on-chip designs Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
What we know after twelve years developing and deploying test data analytics solutions Kenneth M. Butler, Amit Nahar, W. Robert Daasch |
What we know after twelve years developing and deploying test data analytics solutions Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
V. R. Devanathan, Sumant Kale |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Pylon: Towards an integrated customizable volume diagnosis infrastructure Yan Pan, Rao Desineni, Kannan Sekar, Atul Chittora, Sherwin Fernandes, Neerja Bawaskar, John M. Carulli |
Pylon: Towards an integrated customizable volume diagnosis infrastructure Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Ken Hansen |
Details |
|
Discussion Comments:
0
Verification:
Author has
not verified
information
|
|
Automated measurement of defect tolerance in mixed-signal ICs Stephen Sunter, Alessandro Valerio, Riccardo Miglierina |
Automated measurement of defect tolerance in mixed-signal ICs Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Chun-Kai Hsu, Peter Sarson, Gregor Schatzberger, Friedrich Peter Leisenberger, John M. Carulli Jr., Siddhartha Siddhartha, Kwang-Ting Cheng |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Harnessing process variations for optimizing wafer-level probe-test flow Ali Ahmadi, Constantinos Xanthopoulos, Amit Nahar, Bob Orr, Michael Pas, Yiorgos Makris |
Harnessing process variations for optimizing wafer-level probe-test flow Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Logic characterization vehicle design reflection via layout rewiring Phillip Fynan, Zeye Liu, Benjamin Niewenhuis, Soumya Mittal, Marcin Strajwas, R. D. (Shawn) Blanton |
Logic characterization vehicle design reflection via layout rewiring Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Upper-bound computation for optimal retargeting in IEEE1687 networks Farrokh Ghani Zadegan, Rene Krenz-Baath, Erik Larsson |
Upper-bound computation for optimal retargeting in IEEE1687 networks Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Known-good-die test methods for large, thin, high-power digital devices Dave Armstrong, Gary Maier |
Known-good-die test methods for large, thin, high-power digital devices Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Analog fault coverage improvement using final-test dynamic part average testing Wim Dobbelaere, Ronny Vanhooren, Willy De Man, Koen Matthijs, Anthony Coyette, Baris Esen, Georges G. E. Gielen |
Analog fault coverage improvement using final-test dynamic part average testing Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
I-Q signal generation techniques for communication IC testing and ATE systems Masahiro Murakami, Haruo Kobayashi, Shaiful Nizam Bin Mohyar, Osamu Kobayashi, Takahiro Miki, Junya Kojima |
I-Q signal generation techniques for communication IC testing and ATE systems Details |
|
Author Comments:
Discussion Comments:
0
Sharing:
Research produced no artifacts
Verification:
Authors have
verified
information
|
|
Suvadeep Banerjee, Abhijit Chatterjee, Jacob A. Abraham |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Machine learning-based defense against process-aware attacks on Industrial Control Systems Anastasis Keliris, Hossein Salehghaffari, Brian R. Cairl, Prashanth Krishnamurthy, Michail Maniatakos, Farshad Khorrami |
Machine learning-based defense against process-aware attacks on Industrial Control Systems Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays Insik Yoon, Ashwin Chintaluri, Arijit Raychowdhury |
EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Testing of interposer-based 2.5D integrated circuits Ran Wang, Krishnendu Chakrabarty |
Testing of interposer-based 2.5D integrated circuits Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Advanced test methodology for complex SoCs Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Ayub Abdollahian |
Advanced test methodology for complex SoCs Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Effective DC fault models and testing approach for open defects in analog circuits Baris Esen, Anthony Coyette, Georges G. E. Gielen, Wim Dobbelaere, Ronny Vanhooren |
Effective DC fault models and testing approach for open defects in analog circuits Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
A novel diagnostic test generation methodology and its application in production failure isolation M. Enamul Amyeen, Dongok Kim, Maheshwar Chandrasekar, Mohammad Noman, Srikanth Venkataraman, Anurag Jain, Neha Goel, Ramesh Sharma |
A novel diagnostic test generation methodology and its application in production failure isolation Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Barry John Muldrey, Sabyasachi Deyati, Abhijit Chatterjee |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Statistical outlier screening as a test solution health monitor David Shaw, Dirk Hoops, Kenneth M. Butler, Amit Nahar |
Statistical outlier screening as a test solution health monitor Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Fault simulation for analog test coverage Jyotsna Sequeira, Suriyaprakash Natarajan, Prashant Goteti, Nitin Chaudhary |
Fault simulation for analog test coverage Details |
|
Author Comments:
Discussion Comments:
0
Sharing:
Not able to share produced artifacts
Verification:
Authors have
verified
information
|
|
SERDES external loopback test using production parametric-test hardware Shalini Arora, Aman Aflaki, Sounil Biswas, Masashi Shimanouchi |
SERDES external loopback test using production parametric-test hardware Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Online slack-time binning for IO-registered die-to-die interconnects Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng |
Online slack-time binning for IO-registered die-to-die interconnects Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Plenary keynote address Tuesday: The business of test: Test and semiconductor economics Walden C. Rhines |
Plenary keynote address Tuesday: The business of test: Test and semiconductor economics Details |
|
Discussion Comments:
0
Verification:
Author has
not verified
information
|
|
An accurate algorithm for computing mutation coverage in model checking Huina Chao, Huawei Li, Tiancheng Wang, Xiaowei Li, Bo Liu |
An accurate algorithm for computing mutation coverage in model checking Details |
|
Author Comments:
Discussion Comments:
0
Sharing:
Not able to share produced artifacts
Verification:
Authors have
verified
information
|
|
Low cost ultra-pure sine wave generation with self calibration Yuming Zhuang, Akhilesh Kesavan Unnithan, Arun Joseph, Siva Sudani, Benjamin Magstadt, Degang Chen |
Low cost ultra-pure sine wave generation with self calibration Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Recycled FPGA detection using exhaustive LUT path delay characterization Md Mahbub Alam, Mark Tehranipoor, Domenic Forte |
Recycled FPGA detection using exhaustive LUT path delay characterization Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Minimal area test points for deterministic patterns Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer |
Minimal area test points for deterministic patterns Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
A suite of IEEE 1687 benchmark networks Anton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath |
A suite of IEEE 1687 benchmark networks Details |
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
|
Fanchen Zhang, Daphne Hwong, Yi Sun, Allison Garcia, Soha Alhelaly, Geoff Shofner, LeRoy Winemberg, Jennifer Dworak |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Defect tolerance for CNFET-based SRAMs Tianjian Li, Li Jiang, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty |
Defect tolerance for CNFET-based SRAMs Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Takayuki Nakamura, Koji Asami |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Memory repair for high fault rates Panagiota Papavramidou |
Memory repair for high fault rates Details |
Discussion Comments:
0
Verification:
Author has
not verified
information
|
|
|
Cross-layer system reliability assessment framework for hardware faults Alessandro Vallero, Alessandro Savino, Gianfranco Politano, Stefano Di Carlo, Athanasios Chatzidimitriou, Sotiris Tselonis, Manolis Kaliorakis, Dimitris Gizopoulos, Marc Riera, Ramon Canal, Antonio González, Maha Kooli, Alberto Bosio, Giorgio Di Natale |
Cross-layer system reliability assessment framework for hardware faults Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Peter Sarson |
Details |
|
Discussion Comments:
0
Verification:
Author has
not verified
information
|