| Title/Authors | Title | Research Artifacts
[?] A research
artifact is any by-product of a research project that is not
directly included in the published research paper. In Computer
Science research this is often source code and data sets, but
it could also be media, documentation, inputs to proof
assistants, shell-scripts to run experiments, etc.
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Specification, Verification and Design of Evolving Automotive Software: Invited S. Ramesh, Birgit Vogel-Heuser, Wanli Chang, Debayan Roy, Licong Zhang, Samarjit Chakraborty |
Specification, Verification and Design of Evolving Automotive Software: Invited Details |
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A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited Jianping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami |
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited Details |
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Toggle MUX: How X-Optimism Can Lead to Malicious Hardware Christian Krieg, Clifford Wolf, Axel Jantsch, Tanja Zseby |
Toggle MUX: How X-Optimism Can Lead to Malicious Hardware Details |
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Optimized Design of a Human Intranet Network Ali Moin, Pierluigi Nuzzo, Alberto L. Sangiovanni-Vincentelli, Jan M. Rabaey |
Optimized Design of a Human Intranet Network Details |
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Pauli Frames for Quantum Computer Architectures L. Riesebos, X. Fu, Savvas Varsamopoulos, Carmen G. Almudéver, Koen Bertels |
Pauli Frames for Quantum Computer Architectures Details |
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Hierarchical Dataflow Modeling of Iterative Applications Hyesun Hong, Hyunok Oh, Soonhoi Ha |
Hierarchical Dataflow Modeling of Iterative Applications Details |
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Martin Barnasconi, Sumit Adhikari |
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A Clock Tree Optimization Framework with Predictable Timing Quality Rickard Ewetz |
A Clock Tree Optimization Framework with Predictable Timing Quality Details |
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Task Mapping on SMART NoC: Contention Matters, Not the Distance Lei Yang, Weichen Liu, Peng Chen, Nan Guan, Mengquan Li |
Task Mapping on SMART NoC: Contention Matters, Not the Distance Details |
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LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato |
LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations Details |
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Tseng-Yi Chen, Yuan-Hao Chang, Yuan-Hung Kuan, Yu-Ming Chang |
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Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda |
Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks Details |
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Dealing with Uncertainties in Analog/Mixed-Signal Systems: Invited Christoph Grimm, Michael Rathmair |
Dealing with Uncertainties in Analog/Mixed-Signal Systems: Invited Details |
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Safety Guard: Runtime Enforcement for Safety-Critical Cyber-Physical Systems: Invited Meng Wu, Haibo Zeng, Chao Wang, Huafeng Yu |
Safety Guard: Runtime Enforcement for Safety-Critical Cyber-Physical Systems: Invited Details |
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Delay Locking: Security Enhancement of Logic Locking against IC Counterfeiting and Overproduction Yang Xie, Ankur Srivastava |
Delay Locking: Security Enhancement of Logic Locking against IC Counterfeiting and Overproduction Details |
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Bhavya K. Daya, Li-Shiuan Peh, Anantha P. Chandrakasan |
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Yajuan Du, Qiao Li, Liang Shi, Deqing Zou, Hai Jin, Chun Jason Xue |
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Jong Hwan Ko, Burhan Ahmad Mudassar, Taesik Na, Saibal Mukhopadhyay |
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Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs Jianli Chen, Ziran Zhu, Wenxing Zhu, Yao-Wen Chang |
Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs Details |
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ASSURE: Authentication Scheme for SecURE Energy Efficient Non-Volatile Memories Joydeep Rakshit, Kartik Mohanram |
ASSURE: Authentication Scheme for SecURE Energy Efficient Non-Volatile Memories Details |
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Fault-Tolerant Training with On-Line Fault Detection for RRAM-Based Neural Computing Systems Lixue Xia, Mengyun Liu, Xuefei Ning, Krishnendu Chakrabarty, Yu Wang |
Fault-Tolerant Training with On-Line Fault Detection for RRAM-Based Neural Computing Systems Details |
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RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks Mehmet Kayaalp, Khaled N. Khasawneh, Hodjat Asghari Esfeden, Jesse Elwell, Nael B. Abu-Ghazaleh, Dmitry V. Ponomarev, Aamer Jaleel |
RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks Details |
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Adaptation of Enhanced TSV Capacitance as Membrane Property in 3D Brain-inspired Computing System M. Amimul Ehsan, Hongyu An, Zhen Zhou, Yang Yi |
Adaptation of Enhanced TSV Capacitance as Membrane Property in 3D Brain-inspired Computing System Details |
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Deep3: Leveraging Three Levels of Parallelism for Efficient Deep Learning Bita Darvish Rouhani, Azalia Mirhoseini, Farinaz Koushanfar |
Deep3: Leveraging Three Levels of Parallelism for Efficient Deep Learning Details |
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Multi-variable Dynamic Power Management for the GPU Subsystem Pietro Mercati, Raid Ayoub, Michael Kishinevsky, Eric Samson, Marc Beuchat, Francesco Paterna, Tajana Simunic Rosing |
Multi-variable Dynamic Power Management for the GPU Subsystem Details |
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Alfio Di Mauro, Francesco Conti, Luca Benini |
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XFC: A Framework for eXploitable Fault Characterization in Block Ciphers Punit Khanna, Chester Rebeiro, Aritra Hazra |
XFC: A Framework for eXploitable Fault Characterization in Block Ciphers Details |
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A Testbed to Verify the Timing Behavior of Cyber-Physical Systems: Invited Aviral Shrivastava, Mohammadreza Mehrabian, Mohammad Khayatian, Patricia Derler, Hugo A. Andrade, Kevin B. Stanton, Ya-Shian Li-Baboud, Edward Griffor, Marc Weiss, John C. Eidson |
A Testbed to Verify the Timing Behavior of Cyber-Physical Systems: Invited Details |
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Fast Embedding of Constrained Satisfaction Problem to Quantum Annealer with Minimizing Chain Length Juexiao Su, Lei He |
Fast Embedding of Constrained Satisfaction Problem to Quantum Annealer with Minimizing Chain Length Details |
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Rescuing Memristor-based Neuromorphic Design with High Defects Chenchen Liu, Miao Hu, John Paul Strachan, Hai (Helen) Li |
Rescuing Memristor-based Neuromorphic Design with High Defects Details |
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Pin Accessibility-Driven Cell Layout Redesign and Placement Optimization Jaewoo Seo, Jinwook Jung, Sangmin Kim, Youngsoo Shin |
Pin Accessibility-Driven Cell Layout Redesign and Placement Optimization Details |
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Johann Knechtel, Ozgur Sinanoglu |
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Exploring Heterogeneous Algorithms for Accelerating Deep Convolutional Neural Networks on FPGAs Qingcheng Xiao, Yun Liang, Liqiang Lu, Shengen Yan, Yu-Wing Tai |
Exploring Heterogeneous Algorithms for Accelerating Deep Convolutional Neural Networks on FPGAs Details |
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Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery |
Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation Details |
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Path-Specific Functional Timing Verification under Floating and Transition Modes of Operation Chun-Ning Lai, Jie-Hong R. Jiang |
Path-Specific Functional Timing Verification under Floating and Transition Modes of Operation Details |
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Crossroads: Time-Sensitive Autonomous Intersection Management Technique Edward Andert, Mohammad Khayatian, Aviral Shrivastava |
Crossroads: Time-Sensitive Autonomous Intersection Management Technique Details |
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A Kernel Decomposition Architecture for Binary-weight Convolutional Neural Networks Hyeonuk Kim, Jaehyeong Sim, Yeongjae Choi, Lee-Sup Kim |
A Kernel Decomposition Architecture for Binary-weight Convolutional Neural Networks Details |
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Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques Cedric Killian, Daniel Chillet, Sébastien Le Beux, Van-Dung Pham, Olivier Sentieys, Ian O'Connor |
Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques Details |
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Deep Reinforcement Learning for Building HVAC Control Tianshu Wei, Yanzhi Wang, Qi Zhu |
Deep Reinforcement Learning for Building HVAC Control Details |
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TrojanGuard: Simple and Effective Hardware Trojan Mitigation Techniques for Pipelined MPSoCs Amin Malekpour, Roshan G. Ragel, Aleksandar Ignjatovic, Sri Parameswaran |
TrojanGuard: Simple and Effective Hardware Trojan Mitigation Techniques for Pipelined MPSoCs Details |
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Statistical Pattern Based Modeling of GPU Memory Access Streams Reena Panda, Xinnian Zheng, Jiajun Wang, Andreas Gerstlauer, Lizy K. John |
Statistical Pattern Based Modeling of GPU Memory Access Streams Details |
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In Quest of the Next Information Processing Substrate: Extended Abstract: Invited Suman Datta, Alan C. Seabaugh, Michael T. Niemier, Arijit Raychowdhury, Darrell Schlom, Debdeep Jena, Grace Xing, H.-S. Philip Wong, Eric Pop, Sayeef S. Salahuddin, Sumeet Kumar Gupta, Supratik Guha |
In Quest of the Next Information Processing Substrate: Extended Abstract: Invited Details |
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Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-Learning Mohamad Baker Alawieh, Fa Wang, Xin Li |
Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-Learning Details |
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Aayush Ankit, Abhronil Sengupta, Priyadarshini Panda, Kaushik Roy |
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Cooperative DVFS for energy-efficient HEVC decoding on embedded CPU-GPU architecture Fan Gong, Lei Ju, Deshan Zhang, Mengying Zhao, Zhiping Jia |
Cooperative DVFS for energy-efficient HEVC decoding on embedded CPU-GPU architecture Details |
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Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang |
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Making DRAM Stronger Against Row Hammering Mungyu Son, Hyunsun Park, Junwhan Ahn, Sungjoo Yoo |
Making DRAM Stronger Against Row Hammering Details |
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Exploiting Parallelism for Convolutional Connections in Processing-In-Memory Architecture Yi Wang, Mingxu Zhang, Jing Yang |
Exploiting Parallelism for Convolutional Connections in Processing-In-Memory Architecture Details |
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3 Channel Dependency-Based Power Model for Mobile AMOLED Displays Seongwoo Hong, Suk-Won Kim, Young-Jin Kim |
3 Channel Dependency-Based Power Model for Mobile AMOLED Displays Details |
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Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization Seungwon Kim, SangGi Do, Seokhyeong Kang |
Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization Details |
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Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches Dawei Li, Kaicheng Zhang, Akhil Guliani, Seda Ogrenci Memik |
Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches Details |
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PriSearch: Efficient Search on Private Data M. Sadegh Riazi, Ebrahim M. Songhori, Farinaz Koushanfar |
PriSearch: Efficient Search on Private Data Details |
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Age-aware Logic and Memory Co-Placement for RRAM-FPGAs Yuan Xue, Chengmo Yang, Jingtong Hu |
Age-aware Logic and Memory Co-Placement for RRAM-FPGAs Details |
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TraPL: Track Planning of Local Congestion for Global Routing Daohang Shi, Azadeh Davoodi |
TraPL: Track Planning of Local Congestion for Global Routing Details |
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Ying Wang, Huawei Li, Xiaowei Li |
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MOCA: an Inter/Intra-Chip Optical Network for Memory Zhehui Wang, Zhengbin Pang, Peng Yang, Jiang Xu, Xuanqi Chen, Rafael K. V. Maeda, Zhifei Wang, Luan H. K. Duong, Haoran Li, Zhe Wang |
MOCA: an Inter/Intra-Chip Optical Network for Memory Details |
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Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach Chun-Hao Lai, Jishen Zhao, Chia-Lin Yang |
Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach Details |
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Error Propagation Aware Timing Relaxation For Approximate Near Threshold Computing Anteneh Gebregiorgis, Saman Kiamehr, Mehdi Baradaran Tahoori |
Error Propagation Aware Timing Relaxation For Approximate Near Threshold Computing Details |
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Correlated Rare Failure Analysis via Asymptotic Probability Evaluation Jun Tao, Handi Yu, Dian Zhou, Yangfeng Su, Xuan Zeng, Xin Li |
Correlated Rare Failure Analysis via Asymptotic Probability Evaluation Details |
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Cross-level Monte Carlo Framework for System Vulnerability Evaluation against Fault Attack Meng Li, Liangzhen Lai, Vikas Chandra, David Z. Pan |
Cross-level Monte Carlo Framework for System Vulnerability Evaluation against Fault Attack Details |
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Phase-driven Learning-based Dynamic Reliability Management For Multi-core Processors Zhiyuan Yang, Caleb Serafy, Tiantao Lu, Ankur Srivastava |
Phase-driven Learning-based Dynamic Reliability Management For Multi-core Processors Details |
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Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking Andrew Becker, Wei Hu, Yu Tai, Philip Brisk, Ryan Kastner, Paolo Ienne |
Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking Details |
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Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann |
Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage Details |
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CFPU: Configurable Floating Point Multiplier for Energy-Efficient Computing Mohsen Imani, Daniel Peroni, Tajana Rosing |
CFPU: Configurable Floating Point Multiplier for Energy-Efficient Computing Details |
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A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology Biying Xu, Shaolan Li, Nan Sun, David Z. Pan |
A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology Details |
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Negar Reiskarimian, Linxiao Zhang, Harish Krishnaswamy |
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A New Paradigm for Synthesis of Linear Decompressors Emil Gizdarski, Peter Wohl, John A. Waicukauski |
A New Paradigm for Synthesis of Linear Decompressors Details |
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Louis Lintereur |
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Wei Zuo, Louis-Noël Pouchet, Andrey Ayupov, Taemin Kim, Chung-Wei Lin, Shinichi Shiraishi, Deming Chen |
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Test Methodology for Dual-rail Asynchronous Circuits Kuan-Yen Huang, Ting-Yu Shen, Chien-Mo James Li |
Test Methodology for Dual-rail Asynchronous Circuits Details |
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A New Stochastic Computing Multiplier with Application to Deep Convolutional Neural Networks Hyeon Uk Sim, Jongeun Lee |
A New Stochastic Computing Multiplier with Application to Deep Convolutional Neural Networks Details |
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Derong Liu, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan |
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Towards Aging-Induced Approximations Hussam Amrouch, Behnam Khaleghi, Andreas Gerstlauer, Jörg Henkel |
Towards Aging-Induced Approximations Details |
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Group Scissor: Scaling Neuromorphic Computing Design to Large Neural Networks Yandan Wang, Wei Wen, Beiye Liu, Donald M. Chiarulli, Hai (Helen) Li |
Group Scissor: Scaling Neuromorphic Computing Design to Large Neural Networks Details |
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Dynamic Platforms for Uncertainty Management in Future Automotive E/E Architectures: Invited Philipp Mundhenk, Ghizlane Tibba, Licong Zhang, Felix Reimann, Debayan Roy, Samarjit Chakraborty |
Dynamic Platforms for Uncertainty Management in Future Automotive E/E Architectures: Invited Details |
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Coupled circuit/EM simulation for radio frequency circuits Kai Bittner, Hans Georg Brachtendorf, Wim Schoenmaker, Pascal Reynier |
Coupled circuit/EM simulation for radio frequency circuits Details |
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Energy-Aware Standby-Sparing on Heterogeneous Multicore Systems Abhishek Roy, Hakan Aydin, Dakai Zhu |
Energy-Aware Standby-Sparing on Heterogeneous Multicore Systems Details |
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QuAd: Design and Analysis of Quality-Area Optimal Low-Latency Approximate Adders Muhammad Abdullah Hanif, Rehan Hafiz, Osman Hasan, Muhammad Shafique |
QuAd: Design and Analysis of Quality-Area Optimal Low-Latency Approximate Adders Details |
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Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique Tianjian Li, Xiangyu Bi, Naifeng Jing, Xiaoyao Liang, Li Jiang |
Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique Details |
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Accelerating Graph Community Detection with Approximate Updates via an Energy-Efficient NoC Karthi Duraisamy, Hao Lu, Partha Pratim Pande, Ananth Kalyanaraman |
Accelerating Graph Community Detection with Approximate Updates via an Energy-Efficient NoC Details |
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Analyzing Hardware Based Malware Detectors Nisarg Patel, Avesta Sasan, Houman Homayoun |
Analyzing Hardware Based Malware Detectors Details |
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Instruction-Level Data Isolation for the Kernel on ARM Yeongpil Cho, Donghyun Kwon, Yunheung Paek |
Instruction-Level Data Isolation for the Kernel on ARM Details |
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Estimation of Safe Sensor Measurements of Autonomous System Under Attack Raj Gautam Dutta, Xiaolong Guo, Teng Zhang, Kevin A. Kwiat, Charles A. Kamhoua, Laurent Njilla, Yier Jin |
Estimation of Safe Sensor Measurements of Autonomous System Under Attack Details |
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Minimizing Cluster Number with Clip Shifting in Hotspot Pattern Classification Kuan-Jung Chen, Yu-Kai Chuang, Bo-Yi Yu, Shao-Yun Fang |
Minimizing Cluster Number with Clip Shifting in Hotspot Pattern Classification Details |
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Ivory: Early-Stage Design Space Exploration Tool for Integrated Voltage Regulators An Zou, Jingwen Leng, Yazhou Zu, Tao Tong, Vijay Janapa Reddi, David M. Brooks, Gu-Yeon Wei, Xuan Zhang |
Ivory: Early-Stage Design Space Exploration Tool for Integrated Voltage Regulators Details |
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Ivory: Early-Stage Design Space Exploration Tool for Integrated Voltage Regulators
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A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits Niranjan Kulkarni, Aykut Dengi, Sarma B. K. Vrudhula |
A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits Details |
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LiveSynth: Towards an Interactive Synthesis Flow Rafael Trapani Possignolo, Jose Renau |
LiveSynth: Towards an Interactive Synthesis Flow Details |
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Fogging Effect Aware Placement in Electron Beam Lithography Yu-Chen Huang, Yao-Wen Chang |
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Modeling the Effects of AUTOSAR Overheads on Application Timing and Schedulability Manish Chauhan, Rodolfo Pellizzoni, Krzysztof Czarnecki |
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ArchEx: An Extensible Framework for the Exploration of Cyber-Physical System Architectures Dmitrii Kirov, Pierluigi Nuzzo, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli |
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Energy-Efficient Execution for Repetitive App Usages on big.LITTLE Architectures Xianfeng Li, Guikang Chen, Wen Wen |
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No-Jump-into-Basic-Block: Enforce Basic Block CFI on the Fly for Real-world Binaries Wenjian He, Sanjeev Das, Wei Zhang, Yang Liu |
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Extensibility-Driven Automotive In-Vehicle Architecture Design: Invited Qi Zhu, Hengyi Liang, Licong Zhang, Debayan Roy, Wenchao Li, Samarjit Chakraborty |
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An Efficient Memristor-based Distance Accelerator for Time Series Data Mining on Data Centers Xiaowei Xu, Dewen Zeng, Wenyao Xu, Yiyu Shi, Yu Hu |
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Retiming of Two-Phase Latch-Based Resilient Circuits Hsiao-Lun Wang, Minghe Zhang, Peter A. Beerel |
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Advances in Formal Methods for the Design of Analog/Mixed-Signal Systems: Invited Vladimir Dubikhin, Chris J. Myers, Danil Sokolov, Ioannis Syranidis, Alexandre Yakovlev |
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Template Aware Coverage: Taking Coverage Analysis to the Next Level Raviv Gal, Einat Kermany, Bilal Saleh, Avi Ziv, Michael L. Behm, Bryan G. Hickerson |
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Learning to Produce Direct Tests for Security Verification Using Constrained Process Discovery Kuo-Kai Hsieh, Li-C. Wang, Wen Chen, Jayanta Bhadra |
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Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect Jiangyuan Gu, Shouyi Yin, Shaojun Wei |
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SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits Deepashree Sengupta, Farhana Sharmin Snigdha, Jiang Hu, Sachin S. Sapatnekar |
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Extensibility in Automotive Security: Current Practice and Challenges: Invited Sandip Ray, Wen Chen, Jayanta Bhadra, Mohammad Abdullah Al Faruque |
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Developing Dynamic Profiling and Debugging Support in OpenCL for FPGAs Anshuman Verma, Huiyang Zhou, Skip Booth, Robbie King, James Coole, Andy Keep, John Marshall, Wu-chun Feng |
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Pascal Sasdrich, Tim Güneysu |
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Hierarchical Reversible Logic Synthesis Using LUTs Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli |
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Statistical Error Analysis for Low Power Approximate Adders Muhammad Kamran Ayub, Osman Hasan, Muhammad Shafique |
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Improving Performance and Lifetime of Large-Page NAND Storages Using Erase-Free Subpage Programming Myungsuk Kim, Jaehoon Lee, Sungjin Lee, Jisung Park, Jihong Kim |
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LibAbs: An Efficient and Accurate Timing Macro-Modeling Algorithm for Large Hierarchical Designs Tin-Yin Lai, Tsung-Wei Huang, Martin D. F. Wong |
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Power and Area Efficient Hold Time Fixing by Free Metal Segment Allocation Wei-Lun Chiu, Iris Hui-Ru Jiang, Chien-Pang Lu, Yu-Tung Chang |
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A Discrete Model for Networked Labs-on-Chips: Linking the Physical World to Design Automation Andreas Grimmer, Werner Haselmayr, Andreas Springer, Robert Wille |
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Power-aware Performance Tuning of GPU Applications Through Microbenchmarking Nicola Bombieri, Federico Busato, Franco Fummi |
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InCheck: An In-application Recovery Scheme for Soft Errors Moslem Didehban, Sai Ram Dheeraj Lokam, Aviral Shrivastava |
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Leveraging Compiler Optimizations to Reduce Runtime Fault Recovery Overhead Fateme S. Hosseini, Pouya Fotouhi, Chengmo Yang, Guang R. Gao |
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FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible FPGAs Shuo Wang, Yun Liang, Wei Zhang |
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DIMP: A Low-Cost Diversity Metric Based on Circuit Path Analysis Sergi Alcaide, Carles Hernández, Antoni Roca, Jaume Abella |
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Maximizing Forward Progress with Cache-aware Backup for Self-powered Non-volatile Processors Jing Li, Mengying Zhao, Lei Ju, Chun Jason Xue, Zhiping Jia |
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Latency-Aware Packet Processing on CPU-GPU Heterogeneous Systems Arian Maghazeh, Unmesh D. Bordoloi, Usman Dastgeer, Alexandru Andrei, Petru Eles, Zebo Peng |
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Incorporating the Role of Stress on Electromigration in Power Grids with Via Arrays Vivek Mishra, Palkesh Jain, Sravan K. Marella, Sachin S. Sapatnekar |
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Mengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann |
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Dadu: Accelerating Inverse Kinematics for High-DOF Robots Shiqi Lian, Yinhe Han, Ying Wang, Yungang Bao, Hang Xiao, Xiaowei Li, Ninghui Sun |
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Ya Wang, Wenrui Zhang, Peng Li, Jian Gong |
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TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks Ming Cheng, Lixue Xia, Zhenhua Zhu, Yi Cai, Yuan Xie, Yu Wang, Huazhong Yang |
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On Characterizing Near-Threshold SRAM Failures in FinFET Technology Shrikanth Ganapathy, John Kalamatianos, Keith Kasprak, Steven Raasch |
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Formal Techniques for Effective Co-verification of Hardware/Software Co-designs Rajdeep Mukherjee, Mitra Purandare, Raphael Polig, Daniel Kroening |
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Towards Full-System Energy-Accuracy Tradeoffs: A Case Study of An Approximate Smart Camera System Arnab Raha, Vijay Raghunathan |
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Detailed Placement for Two-Dimensional Directed Self-Assembly Technology Zhi-Wen Lin, Yao-Wen Chang |
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Shuo-Han Chen, Yen-Ting Chen, Hsin-Wen Wei, Wei-Kuan Shih |
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Yanan Lu, Leibo Liu, Yangdong Deng, Jian Weng, Zhaoshi Li, Chenchen Deng, Shaojun Wei |
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Exploiting Thread and Data Level Parallelism for Ultimate Parallel SystemC Simulation Tim Schmidt, Guantao Liu, Rainer Dömer |
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A Systems Approach to Computing in Beyond CMOS Fabrics: Invited Ameya Patil, Naresh R. Shanbhag, Lav R. Varshney, Eric Pop, H.-S. Philip Wong, Subhasish Mitra, Jan M. Rabaey, Jeffrey A. Weldon, Larry T. Pileggi, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young |
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Low-overhead Aging-aware Resource Management on Embedded GPUs Haeseung Lee, Muhammad Shafique, Mohammad Abdullah Al Faruque |
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Closing the Accuracy Gap of Static Performance Analysis of Asynchronous Circuits Cheng-Yu Shih, Chun-Hong Shih, Jie-Hong R. Jiang |
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Bandwidth Optimization Through On-Chip Memory Restructuring for HLS Jason Cong, Peng Wei, Cody Hao Yu, Peipei Zhou |
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ObfusCADe: Obfuscating Additive Manufacturing CAD Models Against Counterfeiting: Invited Nikhil Gupta, Fei Chen, Nektarios Georgios Tsoutsos, Michail Maniatakos |
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Disturbance Aware Memory Partitioning for Parallel Data Access in STT-RAM Shouyi Yin, Zhicong Xie, Shaojun Wei |
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Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs Xuechao Wei, Cody Hao Yu, Peng Zhang, Youxiang Chen, Yuxin Wang, Han Hu, Yun Liang, Jason Cong |
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Towards Design and Automation of Hardware-Friendly NOMA Receiver with Iterative Multi-User Detection Muhammad Adeel Pasha, Momin Uppal, Muhammad Hassan Ahmed, Muhammad Aimal Rehman, Muhammad Awais Bin Altaf |
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A Novel ReRAM-based Main Memory Structure for Optimizing Access Latency and Reliability Yang Zhang, Dan Feng, Jingning Liu, Wei Tong, Bing Wu, Caihua Fang |
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Tianyu Jia, Russ Joseph, Jie Gu |
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A-TEAM: Automatic template-based assertion miner Alessandro Danese, Nicolò Dalla Riva, Graziano Pravadelli |
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LSC: A Large-Scale Consensus-Based Clustering Algorithm for High-Performance FPGAs Love Singhal, Mahesh A. Iyer, Saurabh N. Adya |
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Concurrent Pin Access Optimization for Unidirectional Routing Xiaoqing Xu, Yibo Lin, Vinicius S. Livramento, David Z. Pan |
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Optimizing Message Routing and Scheduling in Automotive Mixed-Criticality Time-Triggered Networks Fedor Smirnov, Michael Glaß, Felix Reimann, Jürgen Teich |
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Optimal Circuits for Parallel Bit Reversal Ren Chen, Viktor K. Prasanna |
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Real-Time Multi-Scale Pedestrian Detection for Driver Assistance Systems Maryam Hemmati, Morteza Biglari-Abhari, Smaïl Niar, Stevan Berber |
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Qinghang Zhao, Yongpan Liu, Wenyu Sun, Jiaqing Zhao, Hailong Yao, Xiaojun Guo, Huazhong Yang |
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Chen Zhou, Keshab K. Parhi, Chris H. Kim |
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Hardware ODE Solvers using Stochastic Circuits Siting Liu, Jie Han |
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EDiFy: An Execution time Distribution Finder Boudewijn Braams, Sebastian Altmeyer, Andy D. Pimentel |
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A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications Sebastian Haas, Tobias Seifert, Benedikt Nöthen, Stefan Scholze, Sebastian Höppner, Andreas Dixius, Esther Pérez Adeva, Thomas R. Augustin, Friedrich Pauls, Sadia Moriam, Mattis Hasler, Erik Fischer, Yong Chen, Emil Matús, Georg Ellguth, Stephan Hartmann, Stefan Schiefer, Love Cederström, Dennis Walter, Stephan Henker, Stefan Hänzsche, Johannes Uhlig, Holger Eisenreich, Stefan Weithoffer, Norbert Wehn, René Schüffny, Christian Mayr, Gerhard P. Fettweis |
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Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning Haoyu Yang, Jing Su, Yi Zou, Bei Yu, Evangeline F. Y. Young |
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Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond Jian Kuang, Evangeline F. Y. Young |
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Peng Ouyang, Shouyi Yin, Shaojun Wei |
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An Architecture for Learning Stream Distributions with Application to RNG Testing Alric Althoff, Ryan Kastner |
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Compiler Techniques to Reduce the Synchronization Overhead of GPU Redundant Multithreading Manish Gupta, Daniel Lowell, John Kalamatianos, Steven Raasch, Vilas Sridharan, Dean M. Tullsen, Rajesh K. Gupta |
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LO-FAT: Low-Overhead Control Flow ATtestation in Hardware Ghada Dessouky, Shaza Zeitouni, Thomas Nyman, Andrew Paverd, Lucas Davi, Patrick Koeberl, N. Asokan, Ahmad-Reza Sadeghi |
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Accelerator Design for Deep Learning Training: Extended Abstract: Invited Ankur Agrawal, Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Jinwook Oh, Sunil Shukla, Viji Srinivasan, Swagath Venkataramani, Wei Zhang |
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FFD: A Framework for Fake Flash Detection Zimu Guo, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte |
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A Comprehensive Framework for Synthesizing Stencil Algorithms on FPGAs using OpenCL Model Shuo Wang, Yun Liang |
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Co-training of Feature Extraction and Classification using Partitioned Convolutional Neural Networks Wei-Yu Tsai, Jinhang Choi, Tulika Parija, Priyanka Gomatam, Chita R. Das, John Sampson, Vijaykrishnan Narayanan |
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Fast and Energy-Efficient Digital Filters for Signal Conditioning in Low-Power Microcontrollers Carlos Moreno, Sebastian Fischmeister |
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Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design Gengjie Chen, Jian Kuang, Zhiliang Zeng, Hang Zhang, Evangeline F. Y. Young, Bei Yu |
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HyCUBE: A CGRA with Reconfigurable Single-cycle Multi-hop Interconnect Manupa Karunaratne, Aditi Kulkarni Mohite, Tulika Mitra, Li-Shiuan Peh |
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iClaire: A Fast and General Layout Pattern Classification Algorithm Wei-Chun Chang, Iris Hui-Ru Jiang, Yen-Ting Yu, Wei-Fang Liu |
iClaire: A Fast and General Layout Pattern Classification Algorithm Details |
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Network Synthesis for Database Processing Units Andrea Lottarini, Stephen A. Edwards, Kenneth A. Ross, Martha A. Kim |
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Optimizing Memory Efficiency for Convolution Kernels on Kepler GPUs Xiaoming Chen, Jianxu Chen, Danny Z. Chen, Xiaobo Sharon Hu |
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A Spectral Graph Sparsification Approach to Scalable Vectorless Power Grid Integrity Verification Zhiqiang Zhao, Zhuo Feng |
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Secure Information Flow Verification with Mutable Dependent Types Andrew Ferraiuolo, Weizhe Hua, Andrew C. Myers, G. Edward Suh |
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HALWPE: Hardware-Assisted Light Weight Performance Estimation for GPUs Kenneth O'Neal, Philip Brisk, Emily Shriver, Michael Kishinevsky |
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Graph-Based Logic Bit Slicing for Datapath-Aware Placement Chau-Chin Huang, Bo-Qiao Lin, Hsin-Ying Lee, Yao-Wen Chang, Kuo-Sheng Wu, Jun-Zhi Yang |
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On Quality Trade-off Control for Approximate Computing Using Iterative Training Chengwen Xu, Xiangyu Wu, Wenqi Yin, Qiang Xu, Naifeng Jing, Xiaoyao Liang, Li Jiang |
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Ultra-Efficient Processing In-Memory for Data Intensive Applications Mohsen Imani, Saransh Gupta, Tajana Rosing |
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SmartSwap: High-Performance and User Experience Friendly Swapping in Mobile Systems Xiao Zhu, Duo Liu, Kan Zhong, Jinting Ren, Tao Li |
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A 700fps Optimized Coarse-to-Fine Shape Searching Based Hardware Accelerator for Face Alignment Qiang Wang, Leibo Liu, Wenping Zhu, Huiyu Mo, Chenchen Deng, Shaojun Wei |
A 700fps Optimized Coarse-to-Fine Shape Searching Based Hardware Accelerator for Face Alignment Details |
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Cryo-CMOS Electronic Control for Scalable Quantum Computing: Invited Fabio Sebastiano, Harald Homulle, Bishnu Patra, Rosario M. Incandela, Jeroen P. G. van Dijk, Lin Song, Masoud Babaie, Andrei Vladimirescu, Edoardo Charbon |
Cryo-CMOS Electronic Control for Scalable Quantum Computing: Invited Details |
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Efficient Bayesian Yield Optimization Approach for Analog and SRAM Circuits Mengshuo Wang, Fan Yang, Changhao Yan, Xuan Zeng, Xiangdong Hu |
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Toss-up Wear Leveling: Protecting Phase-Change Memories from Inconsistent Write Patterns Xian Zhang, Guangyu Sun |
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Enabling Write-Reduction Strategy for Journaling File Systems over Byte-addressable NVRAM Tseng-Yi Chen, Yuan-Hao Chang, Shuo-Han Chen, Chih-Ching Kuo, Ming-Chang Yang, Hsin-Wen Wei, Wei-Kuan Shih |
Enabling Write-Reduction Strategy for Journaling File Systems over Byte-addressable NVRAM Details |
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