Design Automation Conference, DAC 2017


Title/Authors Title Research Artifacts
[?] A research artifact is any by-product of a research project that is not directly included in the published research paper. In Computer Science research this is often source code and data sets, but it could also be media, documentation, inputs to proof assistants, shell-scripts to run experiments, etc.
Details

Specification, Verification and Design of Evolving Automotive Software: Invited

S. Ramesh, Birgit Vogel-Heuser, Wanli Chang, Debayan Roy, Licong Zhang, Samarjit Chakraborty

Specification, Verification and Design of Evolving Automotive Software: Invited

Details
Discussion Comments: 0
Verification: Authors have not verified information

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited

Jianping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited

Details
Discussion Comments: 0
Verification: Authors have not verified information

Toggle MUX: How X-Optimism Can Lead to Malicious Hardware

Christian Krieg, Clifford Wolf, Axel Jantsch, Tanja Zseby

Toggle MUX: How X-Optimism Can Lead to Malicious Hardware

Details
Discussion Comments: 0
Verification: Authors have not verified information

Optimized Design of a Human Intranet Network

Ali Moin, Pierluigi Nuzzo, Alberto L. Sangiovanni-Vincentelli, Jan M. Rabaey

Optimized Design of a Human Intranet Network

Details
Discussion Comments: 0
Verification: Authors have not verified information

Pauli Frames for Quantum Computer Architectures

L. Riesebos, X. Fu, S. Varsamopoulos, Carmen G. Almudéver, Koen Bertels

Pauli Frames for Quantum Computer Architectures

Details
Discussion Comments: 0
Verification: Authors have not verified information

Hierarchical Dataflow Modeling of Iterative Applications

Hyesun Hong, Hyunok Oh, Soonhoi Ha

Hierarchical Dataflow Modeling of Iterative Applications

Details
Discussion Comments: 0
Verification: Authors have not verified information

ESL Design in SystemC AMS: Introducing a top-down design methodology for mixed-signal systems: Invited

Martin Barnasconi, Sumit Adhikari

ESL Design in SystemC AMS: Introducing a top-down design methodology for mixed-signal systems: Invited

Details
Discussion Comments: 0
Verification: Authors have not verified information

A Clock Tree Optimization Framework with Predictable Timing Quality

Rickard Ewetz

A Clock Tree Optimization Framework with Predictable Timing Quality

Details
Discussion Comments: 0
Verification: Author has not verified information

Task Mapping on SMART NoC: Contention Matters, Not the Distance

Lei Yang, Weichen Liu, Peng Chen, Nan Guan, Mengquan Li

Task Mapping on SMART NoC: Contention Matters, Not the Distance

Details
Discussion Comments: 0
Verification: Authors have not verified information

LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations

Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato

LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations

Details
Discussion Comments: 0
Verification: Authors have not verified information

VirtualGC: Enabling Erase-free Garbage Collection to Upgrade the Performance of Rewritable SLC NAND Flash Memory

Tseng-Yi Chen, Yuan-Hao Chang, Yuan-Hung Kuan, Yu-Ming Chang

VirtualGC: Enabling Erase-free Garbage Collection to Upgrade the Performance of Rewritable SLC NAND Flash Memory

Details
Discussion Comments: 0
Verification: Authors have not verified information

Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks

Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda

Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks

Details
Discussion Comments: 0
Verification: Authors have not verified information

Dealing with Uncertainties in Analog/Mixed-Signal Systems: Invited

Christoph Grimm, Michael Rathmair

Dealing with Uncertainties in Analog/Mixed-Signal Systems: Invited

Details
Discussion Comments: 0
Verification: Authors have not verified information

Safety Guard: Runtime Enforcement for Safety-Critical Cyber-Physical Systems: Invited

Meng Wu, Haibo Zeng, Chao Wang, Huafeng Yu

Safety Guard: Runtime Enforcement for Safety-Critical Cyber-Physical Systems: Invited

Details
Discussion Comments: 0
Verification: Authors have not verified information

Delay Locking: Security Enhancement of Logic Locking against IC Counterfeiting and Overproduction

Yang Xie, Ankur Srivastava

Delay Locking: Security Enhancement of Logic Locking against IC Counterfeiting and Overproduction

Details
Discussion Comments: 0
Verification: Authors have not verified information

Low-Power On-Chip Network Providing Guaranteed Services for Snoopy Coherent and Artificial Neural Network Systems

Bhavya K. Daya, Li-Shiuan Peh, Anantha P. Chandrakasan

Low-Power On-Chip Network Providing Guaranteed Services for Snoopy Coherent and Artificial Neural Network Systems

Details
Discussion Comments: 0
Verification: Authors have not verified information

Reducing LDPC Soft Sensing Latency by Lightweight Data Refresh for Flash Read Performance Improvement

Yajuan Du, Qiao Li, Liang Shi, Deqing Zou, Hai Jin, Chun Jason Xue

Reducing LDPC Soft Sensing Latency by Lightweight Data Refresh for Flash Read Performance Improvement

Details
Discussion Comments: 0
Verification: Authors have not verified information

Design of an Energy-Efficient Accelerator for Training of Convolutional Neural Networks using Frequency-Domain Computation

Jong Hwan Ko, Burhan Ahmad Mudassar, Taesik Na, Saibal Mukhopadhyay

Design of an Energy-Efficient Accelerator for Training of Convolutional Neural Networks using Frequency-Domain Computation

Details
Discussion Comments: 0
Verification: Authors have not verified information

Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs

Jianli Chen, Ziran Zhu, Wenxing Zhu, Yao-Wen Chang

Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs

Details
Discussion Comments: 0
Verification: Authors have not verified information

ASSURE: Authentication Scheme for SecURE Energy Efficient Non-Volatile Memories

Joydeep Rakshit, Kartik Mohanram

ASSURE: Authentication Scheme for SecURE Energy Efficient Non-Volatile Memories

Details
Discussion Comments: 0
Verification: Authors have not verified information

Fault-Tolerant Training with On-Line Fault Detection for RRAM-Based Neural Computing Systems

Lixue Xia, Mengyun Liu, Xuefei Ning, Krishnendu Chakrabarty, Yu Wang

Fault-Tolerant Training with On-Line Fault Detection for RRAM-Based Neural Computing Systems

Details
Discussion Comments: 0
Verification: Authors have not verified information

RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks

Mehmet Kayaalp, Khaled N. Khasawneh, Hodjat Asghari Esfeden, Jesse Elwell, Nael B. Abu-Ghazaleh, Dmitry V. Ponomarev, Aamer Jaleel

RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks

Details
Discussion Comments: 0
Verification: Authors have not verified information

Adaptation of Enhanced TSV Capacitance as Membrane Property in 3D Brain-inspired Computing System

M. Amimul Ehsan, Hongyu An, Zhen Zhou, Yang Yi

Adaptation of Enhanced TSV Capacitance as Membrane Property in 3D Brain-inspired Computing System

Details
Discussion Comments: 0
Verification: Authors have not verified information

Deep3: Leveraging Three Levels of Parallelism for Efficient Deep Learning

Bita Darvish Rouhani, Azalia Mirhoseini, Farinaz Koushanfar

Deep3: Leveraging Three Levels of Parallelism for Efficient Deep Learning

Details
Discussion Comments: 0
Verification: Authors have not verified information

Multi-variable Dynamic Power Management for the GPU Subsystem

Pietro Mercati, Raid Ayoub, Michael Kishinevsky, Eric Samson, Marc Beuchat, Francesco Paterna, Tajana Simunic Rosing

Multi-variable Dynamic Power Management for the GPU Subsystem

Details
Discussion Comments: 0
Verification: Authors have not verified information

An Ultra-Low Power Address-Event Sensor Interface for Energy-Proportional Time-to-Information Extraction

Alfio Di Mauro, Francesco Conti, Luca Benini

An Ultra-Low Power Address-Event Sensor Interface for Energy-Proportional Time-to-Information Extraction

Details
Discussion Comments: 0
Verification: Authors have not verified information

XFC: A Framework for eXploitable Fault Characterization in Block Ciphers

Punit Khanna, Chester Rebeiro, Aritra Hazra

XFC: A Framework for eXploitable Fault Characterization in Block Ciphers

Details
Discussion Comments: 0
Verification: Authors have not verified information

A Testbed to Verify the Timing Behavior of Cyber-Physical Systems: Invited

Aviral Shrivastava, Mohammadreza Mehrabian, Mohammad Khayatian, Patricia Derler, Hugo A. Andrade, Kevin Stanton, Ya-Shian Li-Baboud, Edward Griffor, Marc Weiss, John C. Eidson

A Testbed to Verify the Timing Behavior of Cyber-Physical Systems: Invited

Details
Discussion Comments: 0
Verification: Authors have not verified information

Fast Embedding of Constrained Satisfaction Problem to Quantum Annealer with Minimizing Chain Length

Juexiao Su, Lei He

Fast Embedding of Constrained Satisfaction Problem to Quantum Annealer with Minimizing Chain Length

Details
Discussion Comments: 0
Verification: Authors have not verified information

Rescuing Memristor-based Neuromorphic Design with High Defects

Chenchen Liu, Miao Hu, John Paul Strachan, Hai (Helen) Li

Rescuing Memristor-based Neuromorphic Design with High Defects

Details
Discussion Comments: 0
Verification: Authors have not verified information

Pin Accessibility-Driven Cell Layout Redesign and Placement Optimization

Jaewoo Seo, Jinwook Jung, Sangmin Kim, Youngsoo Shin

Pin Accessibility-Driven Cell Layout Redesign and Placement Optimization

Details
Discussion Comments: 0
Verification: Authors have not verified information

On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity

Johann Knechtel, Ozgur Sinanoglu

On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity

Details
Author Comments:
Discussion Comments: 0
Sharing: Research produced artifacts
Verification: Authors have verified information

Exploring Heterogeneous Algorithms for Accelerating Deep Convolutional Neural Networks on FPGAs

Qingcheng Xiao, Yun Liang, Liqiang Lu, Shengen Yan, Yu-Wing Tai

Exploring Heterogeneous Algorithms for Accelerating Deep Convolutional Neural Networks on FPGAs

Details
Discussion Comments: 0
Verification: Authors have not verified information

Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation

Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David Chinnery

Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation

Details
Author Comments:
Discussion Comments: 0
Sharing: Not able to share produced artifacts
Verification: Authors have verified information

Path-Specific Functional Timing Verification under Floating and Transition Modes of Operation

Chun-Ning Lai, Jie-Hong R. Jiang

Path-Specific Functional Timing Verification under Floating and Transition Modes of Operation

Details
Discussion Comments: 0
Verification: Authors have not verified information

Crossroads: Time-Sensitive Autonomous Intersection Management Technique

Edward Andert, Mohammad Khayatian, Aviral Shrivastava

Crossroads: Time-Sensitive Autonomous Intersection Management Technique

Details
Discussion Comments: 0
Verification: Authors have not verified information

A Kernel Decomposition Architecture for Binary-weight Convolutional Neural Networks

Hyeonuk Kim, Jaehyeong Sim, Yeongjae Choi, Lee-Sup Kim

A Kernel Decomposition Architecture for Binary-weight Convolutional Neural Networks

Details
Discussion Comments: 0
Verification: Authors have not verified information

Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques

Cedric Killian, Daniel Chillet, Sébastien Le Beux, Van-Dung Pham, Olivier Sentieys, Ian O'Connor

Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques

Details
Discussion Comments: 0
Verification: Authors have not verified information

Deep Reinforcement Learning for Building HVAC Control

Tianshu Wei, Yanzhi Wang, Qi Zhu

Deep Reinforcement Learning for Building HVAC Control

Details
Discussion Comments: 0
Verification: Authors have not verified information

TrojanGuard: Simple and Effective Hardware Trojan Mitigation Techniques for Pipelined MPSoCs

Amin Malekpour, Roshan G. Ragel, Aleksandar Ignjatovic, Sri Parameswaran

TrojanGuard: Simple and Effective Hardware Trojan Mitigation Techniques for Pipelined MPSoCs

Details
Discussion Comments: 0
Verification: Authors have not verified information

Statistical Pattern Based Modeling of GPU Memory Access Streams

Reena Panda, Xinnian Zheng, Jiajun Wang, Andreas Gerstlauer, Lizy K. John

Statistical Pattern Based Modeling of GPU Memory Access Streams

Details
Author Comments:
Discussion Comments: 0
Sharing: Not able to share produced artifacts
Verification: Authors have verified information

In Quest of the Next Information Processing Substrate: Extended Abstract: Invited

Suman Datta, Alan Seabaugh, Michael T. Niemier, Arijit Raychowdhury, Darrell Schlom, Debdeep Jena, Grace Xing, H.-S. Philip Wong, Eric Pop, Sayeef Salahuddin, Sumeet Kumar Gupta, Supratik Guha

In Quest of the Next Information Processing Substrate: Extended Abstract: Invited

Details
Discussion Comments: 0
Verification: Authors have not verified information

Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-Learning

Mohamad Baker Alawieh, Fa Wang, Xin Li

Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-Learning

Details
Discussion Comments: 0
Verification: Authors have not verified information

RESPARC: A Reconfigurable and Energy-Efficient Architecture with Memristive Crossbars for Deep Spiking Neural Networks

Aayush Ankit, Abhronil Sengupta, Priyadarshini Panda, Kaushik Roy

RESPARC: A Reconfigurable and Energy-Efficient Architecture with Memristive Crossbars for Deep Spiking Neural Networks

Details
Discussion Comments: 0
Verification: Authors have not verified information

Cooperative DVFS for energy-efficient HEVC decoding on embedded CPU-GPU architecture

Fan Gong, Lei Ju, Deshan Zhang, Mengying Zhao, Zhiping Jia

Cooperative DVFS for energy-efficient HEVC decoding on embedded CPU-GPU architecture

Details
Discussion Comments: 0
Verification: Authors have not verified information

Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes

Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang

Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes

Details
Discussion Comments: 0
Verification: Authors have not verified information

Making DRAM Stronger Against Row Hammering

Mungyu Son, Hyunsun Park, Junwhan Ahn, Sungjoo Yoo

Making DRAM Stronger Against Row Hammering

Details
Discussion Comments: 0
Verification: Authors have not verified information

Exploiting Parallelism for Convolutional Connections in Processing-In-Memory Architecture

Yi Wang, Mingxu Zhang, Jing Yang

Exploiting Parallelism for Convolutional Connections in Processing-In-Memory Architecture

Details
Discussion Comments: 0
Verification: Authors have not verified information

3 Channel Dependency-Based Power Model for Mobile AMOLED Displays

Seongwoo Hong, Suk-Won Kim, Young-Jin Kim

3 Channel Dependency-Based Power Model for Mobile AMOLED Displays

Details
Discussion Comments: 0
Verification: Authors have not verified information

Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization

Seungwon Kim, SangGi Do, Seokhyeong Kang

Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization

Details
Discussion Comments: 0
Verification: Authors have not verified information

Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches

Dawei Li, Kaicheng Zhang, Akhil Guliani, Seda Ogrenci Memik

Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches

Details
Discussion Comments: 0
Verification: Authors have not verified information

PriSearch: Efficient Search on Private Data

M. Sadegh Riazi, Ebrahim M. Songhori, Farinaz Koushanfar

PriSearch: Efficient Search on Private Data

Details
Discussion Comments: 0
Verification: Authors have not verified information

Age-aware Logic and Memory Co-Placement for RRAM-FPGAs

Yuan Xue, Chengmo Yang, Jingtong Hu

Age-aware Logic and Memory Co-Placement for RRAM-FPGAs

Details
Discussion Comments: 0
Verification: Authors have not verified information

TraPL: Track Planning of Local Congestion for Global Routing

Daohang Shi, Azadeh Davoodi

TraPL: Track Planning of Local Congestion for Global Routing

Details
Discussion Comments: 0
Verification: Authors have not verified information

Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR

Ying Wang, Huawei Li, Xiaowei Li

Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR

Details
Discussion Comments: 0
Verification: Authors have not verified information

MOCA: an Inter/Intra-Chip Optical Network for Memory

Zhehui Wang, Zhengbin Pang, Peng Yang, Jiang Xu, Xuanqi Chen, Rafael K. V. Maeda, Zhifei Wang, Luan H. K. Duong, Haoran Li, Zhe Wang

MOCA: an Inter/Intra-Chip Optical Network for Memory

Details
Discussion Comments: 0
Verification: Authors have not verified information

Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach

Chun-Hao Lai, Jishen Zhao, Chia-Lin Yang

Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach

Details
Discussion Comments: 0
Verification: Authors have not verified information

Error Propagation Aware Timing Relaxation For Approximate Near Threshold Computing

Anteneh Gebregiorgis, Saman Kiamehr, Mehdi Baradaran Tahoori

Error Propagation Aware Timing Relaxation For Approximate Near Threshold Computing

Details
Discussion Comments: 0
Verification: Authors have not verified information

Correlated Rare Failure Analysis via Asymptotic Probability Evaluation

Jun Tao, Handi Yu, Dian Zhou, Yangfeng Su, Xuan Zeng, Xin Li

Correlated Rare Failure Analysis via Asymptotic Probability Evaluation

Details
Discussion Comments: 0
Verification: Authors have not verified information

Cross-level Monte Carlo Framework for System Vulnerability Evaluation against Fault Attack

Meng Li, Liangzhen Lai, Vikas Chandra, David Z. Pan

Cross-level Monte Carlo Framework for System Vulnerability Evaluation against Fault Attack

Details
Discussion Comments: 0
Verification: Authors have not verified information

Phase-driven Learning-based Dynamic Reliability Management For Multi-core Processors

Zhiyuan Yang, Caleb Serafy, Tiantao Lu, Ankur Srivastava

Phase-driven Learning-based Dynamic Reliability Management For Multi-core Processors

Details
Discussion Comments: 0
Verification: Authors have not verified information

Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking

Andrew Becker, Wei Hu, Yu Tai, Philip Brisk, Ryan Kastner, Paolo Ienne

Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking

Details
Discussion Comments: 0
Verification: Authors have not verified information

Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage

Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann

Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage

Details
Discussion Comments: 0
Verification: Authors have not verified information

CFPU: Configurable Floating Point Multiplier for Energy-Efficient Computing

Mohsen Imani, Daniel Peroni, Tajana Rosing

CFPU: Configurable Floating Point Multiplier for Energy-Efficient Computing

Details
Discussion Comments: 0
Verification: Authors have not verified information

A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology

Biying Xu, Shaolan Li, Nan Sun, David Z. Pan

A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology

Details
Author Comments:
Discussion Comments: 0
Sharing: Research produced no artifacts
Verification: Authors have verified information

Linear Periodically Time-Varying (LPTV) Circuits Enable New Radio Architectures for Emerging Wireless Communication Paradigms: Extended Abstract: Invited

Negar Reiskarimian, Linxiao Zhang, Harish Krishnaswamy

Linear Periodically Time-Varying (LPTV) Circuits Enable New Radio Architectures for Emerging Wireless Communication Paradigms: Extended Abstract: Invited

Details
Discussion Comments: 0
Verification: Authors have not verified information

A New Paradigm for Synthesis of Linear Decompressors

Emil Gizdarski, Peter Wohl, John A. Waicukauski

A New Paradigm for Synthesis of Linear Decompressors

Details
Author Comments:
Discussion Comments: 0
Sharing: Not able to share produced artifacts
Verification: Authors have verified information

INVITED Challenges and Potential for Incorporating Model-Based Design in Medical Device Development: Extended Abstract

Louis Lintereur

INVITED Challenges and Potential for Incorporating Model-Based Design in Medical Device Development: Extended Abstract

Details
Discussion Comments: 0
Verification: Author has not verified information

Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration

Wei Zuo, Louis-Noël Pouchet, Andrey Ayupov, Taemin Kim, Chung-Wei Lin, Shinichi Shiraishi, Deming Chen

Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration

Details
Discussion Comments: 0
Verification: Authors have not verified information

Test Methodology for Dual-rail Asynchronous Circuits

Kuan-Yen Huang, Ting-Yu Shen, Chien-Mo Li

Test Methodology for Dual-rail Asynchronous Circuits

Details
Discussion Comments: 0
Verification: Authors have not verified information

A New Stochastic Computing Multiplier with Application to Deep Convolutional Neural Networks

Hyeon Uk Sim, Jongeun Lee

A New Stochastic Computing Multiplier with Application to Deep Convolutional Neural Networks

Details
Discussion Comments: 0
Verification: Authors have not verified information

Streak: Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups

Derong Liu, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan

Streak: Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups

Details
Discussion Comments: 0
Verification: Authors have not verified information

Towards Aging-Induced Approximations

Hussam Amrouch, Behnam Khaleghi, Andreas Gerstlauer, Jörg Henkel

Towards Aging-Induced Approximations

Details
Discussion Comments: 0
Verification: Authors have not verified information

Group Scissor: Scaling Neuromorphic Computing Design to Large Neural Networks

Yandan Wang, Wei Wen, Beiye Liu, Donald M. Chiarulli, Hai (Helen) Li

Group Scissor: Scaling Neuromorphic Computing Design to Large Neural Networks

Details
Discussion Comments: 0
Verification: Authors have not verified information

Dynamic Platforms for Uncertainty Management in Future Automotive E/E Architectures: Invited

Philipp Mundhenk, Ghizlane Tibba, Licong Zhang, Felix Reimann, Debayan Roy, Samarjit Chakraborty

Dynamic Platforms for Uncertainty Management in Future Automotive E/E Architectures: Invited

Details
Discussion Comments: 0
Verification: Authors have not verified information

Coupled circuit/EM simulation for radio frequency circuits

Kai Bittner, Hans Georg Brachtendorf, Wim Schoenmaker, Pascal Reynier

Coupled circuit/EM simulation for radio frequency circuits

Details
Discussion Comments: 0
Verification: Authors have not verified information

Energy-Aware Standby-Sparing on Heterogeneous Multicore Systems

Abhishek Roy, Hakan Aydin, Dakai Zhu

Energy-Aware Standby-Sparing on Heterogeneous Multicore Systems

Details
Discussion Comments: 0
Verification: Authors have not verified information

QuAd: Design and Analysis of Quality-Area Optimal Low-Latency Approximate Adders

Muhammad Abdullah Hanif, Rehan Hafiz, Osman Hasan, Muhammad Shafique

QuAd: Design and Analysis of Quality-Area Optimal Low-Latency Approximate Adders

Details
Discussion Comments: 0
Verification: Authors have not verified information

Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique

Tianjian Li, Xiangyu Bi, Naifeng Jing, Xiaoyao Liang, Li Jiang

Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique

Details
Discussion Comments: 0
Verification: Authors have not verified information

Accelerating Graph Community Detection with Approximate Updates via an Energy-Efficient NoC

Karthi Duraisamy, Hao Lu, Partha Pratim Pande, Ananth Kalyanaraman

Accelerating Graph Community Detection with Approximate Updates via an Energy-Efficient NoC

Details
Discussion Comments: 0
Verification: Authors have not verified information

Analyzing Hardware Based Malware Detectors

Nisarg Patel, Avesta Sasan, Houman Homayoun

Analyzing Hardware Based Malware Detectors

Details
Discussion Comments: 0
Verification: Authors have not verified information

Instruction-Level Data Isolation for the Kernel on ARM

Yeongpil Cho, Donghyun Kwon, Yunheung Paek

Instruction-Level Data Isolation for the Kernel on ARM

Details
Discussion Comments: 0
Verification: Authors have not verified information

Estimation of Safe Sensor Measurements of Autonomous System Under Attack

Raj Gautam Dutta, Xiaolong Guo, Teng Zhang, Kevin A. Kwiat, Charles A. Kamhoua, Laurent Njilla, Yier Jin

Estimation of Safe Sensor Measurements of Autonomous System Under Attack

Details
Discussion Comments: 0
Verification: Authors have not verified information

Minimizing Cluster Number with Clip Shifting in Hotspot Pattern Classification

Kuan-Jung Chen, Yu-Kai Chuang, Bo-Yi Yu, Shao-Yun Fang

Minimizing Cluster Number with Clip Shifting in Hotspot Pattern Classification

Details
Discussion Comments: 0
Verification: Authors have not verified information

Ivory: Early-Stage Design Space Exploration Tool for Integrated Voltage Regulators

An Zou, Jingwen Leng, Yazhou Zu, Tao Tong, Vijay Janapa Reddi, David M. Brooks, Gu-Yeon Wei, Xuan Zhang

Ivory: Early-Stage Design Space Exploration Tool for Integrated Voltage Regulators

Details
Author Comments: Ivory: Early-Stage Design Space Exploration Tool for Integrated Voltage Regulators
Discussion Comments: 0
Sharing: Research produced artifacts
Verification: Authors have verified information

A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits

Niranjan Kulkarni, Aykut Dengi, Sarma B. K. Vrudhula

A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits

Details
Discussion Comments: 0
Verification: Authors have not verified information

LiveSynth: Towards an Interactive Synthesis Flow

Rafael Trapani Possignolo, Jose Renau

LiveSynth: Towards an Interactive Synthesis Flow

Details
Discussion Comments: 0
Verification: Authors have not verified information

Fogging Effect Aware Placement in Electron Beam Lithography

Yu-Chen Huang, Yao-Wen Chang

Fogging Effect Aware Placement in Electron Beam Lithography

Details
Discussion Comments: 0
Verification: Authors have not verified information

Modeling the Effects of AUTOSAR Overheads on Application Timing and Schedulability

Manish Chauhan, Rodolfo Pellizzoni, Krzysztof Czarnecki

Modeling the Effects of AUTOSAR Overheads on Application Timing and Schedulability

Details
Discussion Comments: 0
Verification: Authors have not verified information

ArchEx: An Extensible Framework for the Exploration of Cyber-Physical System Architectures

Dmitrii Kirov, Pierluigi Nuzzo, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli

ArchEx: An Extensible Framework for the Exploration of Cyber-Physical System Architectures

Details
Discussion Comments: 0
Verification: Authors have not verified information

Energy-Efficient Execution for Repetitive App Usages on big.LITTLE Architectures

Xianfeng Li, Guikang Chen, Wen Wen

Energy-Efficient Execution for Repetitive App Usages on big.LITTLE Architectures

Details
Discussion Comments: 0
Verification: Authors have not verified information

No-Jump-into-Basic-Block: Enforce Basic Block CFI on the Fly for Real-world Binaries

Wenjian He, Sanjeev Das, Wei Zhang, Yang Liu

No-Jump-into-Basic-Block: Enforce Basic Block CFI on the Fly for Real-world Binaries

Details
Discussion Comments: 0
Verification: Authors have not verified information

Extensibility-Driven Automotive In-Vehicle Architecture Design: Invited

Qi Zhu, Hengyi Liang, Licong Zhang, Debayan Roy, Wenchao Li, Samarjit Chakraborty

Extensibility-Driven Automotive In-Vehicle Architecture Design: Invited

Details
Discussion Comments: 0
Verification: Authors have not verified information

An Efficient Memristor-based Distance Accelerator for Time Series Data Mining on Data Centers

Xiaowei Xu, Dewen Zeng, Wenyao Xu, Yiyu Shi, Yu Hu

An Efficient Memristor-based Distance Accelerator for Time Series Data Mining on Data Centers

Details
Discussion Comments: 0
Verification: Authors have not verified information

Retiming of Two-Phase Latch-Based Resilient Circuits

Hsiao-Lun Wang, Minghe Zhang, Peter A. Beerel

Retiming of Two-Phase Latch-Based Resilient Circuits

Details
Discussion Comments: 0
Verification: Authors have not verified information

Advances in Formal Methods for the Design of Analog/Mixed-Signal Systems: Invited

Vladimir Dubikhin, Chris J. Myers, Danil Sokolov, Ioannis Syranidis, Alexandre Yakovlev

Advances in Formal Methods for the Design of Analog/Mixed-Signal Systems: Invited

Details
Discussion Comments: 0
Verification: Authors have not verified information

Template Aware Coverage: Taking Coverage Analysis to the Next Level

Raviv Gal, Einat Kermany, Bilal Saleh, Avi Ziv, Michael L. Behm, Bryan G. Hickerson

Template Aware Coverage: Taking Coverage Analysis to the Next Level

Details
Discussion Comments: 0
Verification: Authors have not verified information

Learning to Produce Direct Tests for Security Verification Using Constrained Process Discovery

Kuo-Kai Hsieh, Li-C. Wang, Wen Chen, Jayanta Bhadra

Learning to Produce Direct Tests for Security Verification Using Constrained Process Discovery

Details
Discussion Comments: 0
Verification: Authors have not verified information

Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect

Jiangyuan Gu, Shouyi Yin, Shaojun Wei

Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect

Details
Discussion Comments: 0
Verification: Authors have not verified information

SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits

Deepashree Sengupta, Farhana Sharmin Snigdha, Jiang Hu, Sachin S. Sapatnekar

SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits

Details
Discussion Comments: 0
Verification: Authors have not verified information

Extensibility in Automotive Security: Current Practice and Challenges: Invited

Sandip Ray, Wen Chen, Jayanta Bhadra, Mohammad Abdullah Al Faruque

Extensibility in Automotive Security: Current Practice and Challenges: Invited

Details
Discussion Comments: 0
Verification: Authors have not verified information

Developing Dynamic Profiling and Debugging Support in OpenCL for FPGAs

Anshuman Verma, Huiyang Zhou, Skip Booth, Robbie King, James Coole, Andy Keep, John Marshall, Wu-chun Feng

Developing Dynamic Profiling and Debugging Support in OpenCL for FPGAs

Details
Discussion Comments: 0
Verification: Authors have not verified information

Cryptography for Next Generation TLS: Implementing the RFC 7748 Elliptic Curve448 Cryptosystem in Hardware

Pascal Sasdrich, Tim Güneysu

Cryptography for Next Generation TLS: Implementing the RFC 7748 Elliptic Curve448 Cryptosystem in Hardware

Details
Discussion Comments: 0
Verification: Authors have not verified information

Hierarchical Reversible Logic Synthesis Using LUTs

Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli

Hierarchical Reversible Logic Synthesis Using LUTs

Details
Discussion Comments: 0
Verification: Authors have not verified information

Statistical Error Analysis for Low Power Approximate Adders

Muhammad Kamran Ayub, Osman Hasan, Muhammad Shafique

Statistical Error Analysis for Low Power Approximate Adders

Details
Discussion Comments: 0
Verification: Authors have not verified information

Improving Performance and Lifetime of Large-Page NAND Storages Using Erase-Free Subpage Programming

Myungsuk Kim, Jaehoon Lee, Sungjin Lee, Jisung Park, Jihong Kim

Improving Performance and Lifetime of Large-Page NAND Storages Using Erase-Free Subpage Programming

Details
Discussion Comments: 0
Verification: Authors have not verified information

LibAbs: An Efficient and Accurate Timing Macro-Modeling Algorithm for Large Hierarchical Designs

Tin-Yin Lai, Tsung-Wei Huang, Martin D. F. Wong

LibAbs: An Efficient and Accurate Timing Macro-Modeling Algorithm for Large Hierarchical Designs

Details
Discussion Comments: 0
Verification: Authors have not verified information

Power and Area Efficient Hold Time Fixing by Free Metal Segment Allocation

Wei-Lun Chiu, Iris Hui-Ru Jiang, Chien-Pang Lu, Yu-Tung Chang

Power and Area Efficient Hold Time Fixing by Free Metal Segment Allocation

Details
Discussion Comments: 0
Verification: Authors have not verified information

A Discrete Model for Networked Labs-on-Chips: Linking the Physical World to Design Automation

Andreas Grimmer, Werner Haselmayr, Andreas Springer, Robert Wille

A Discrete Model for Networked Labs-on-Chips: Linking the Physical World to Design Automation

Details
Discussion Comments: 0
Verification: Authors have not verified information

Power-aware Performance Tuning of GPU Applications Through Microbenchmarking

Nicola Bombieri, Federico Busato, Franco Fummi

Power-aware Performance Tuning of GPU Applications Through Microbenchmarking

Details
Author Comments:
Discussion Comments: 0
Sharing: Research produced artifacts
Verification: Authors have verified information

InCheck: An In-application Recovery Scheme for Soft Errors

Moslem Didehban, Sai Ram Dheeraj Lokam, Aviral Shrivastava

InCheck: An In-application Recovery Scheme for Soft Errors

Details
Discussion Comments: 0
Verification: Authors have not verified information

Leveraging Compiler Optimizations to Reduce Runtime Fault Recovery Overhead

Fateme S. Hosseini, Pouya Fotouhi, Chengmo Yang, Guang R. Gao

Leveraging Compiler Optimizations to Reduce Runtime Fault Recovery Overhead

Details
Author Comments:
Discussion Comments: 0
Sharing: Research produced artifacts
Verification: Authors have verified information

FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible FPGAs

Shuo Wang, Yun Liang, Wei Zhang

FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible FPGAs

Details
Discussion Comments: 0
Verification: Authors have not verified information

DIMP: A Low-Cost Diversity Metric Based on Circuit Path Analysis

Sergi Alcaide, Carles Hernández, Antoni Roca, Jaume Abella

DIMP: A Low-Cost Diversity Metric Based on Circuit Path Analysis

Details
Discussion Comments: 0
Verification: Authors have not verified information

Maximizing Forward Progress with Cache-aware Backup for Self-powered Non-volatile Processors

Jing Li, Mengying Zhao, Lei Ju, Chun Jason Xue, Zhiping Jia

Maximizing Forward Progress with Cache-aware Backup for Self-powered Non-volatile Processors

Details
Discussion Comments: 0
Verification: Authors have not verified information

Latency-Aware Packet Processing on CPU-GPU Heterogeneous Systems

Arian Maghazeh, Unmesh D. Bordoloi, Usman Dastgeer, Alexandru Andrei, Petru Eles, Zebo Peng

Latency-Aware Packet Processing on CPU-GPU Heterogeneous Systems

Details
Discussion Comments: 0
Verification: Authors have not verified information

Incorporating the Role of Stress on Electromigration in Power Grids with Via Arrays

Vivek Mishra, Palkesh Jain, Sravan K. Marella, Sachin S. Sapatnekar

Incorporating the Role of Stress on Electromigration in Power Grids with Via Arrays

Details
Discussion Comments: 0
Verification: Authors have not verified information

Component-Oriented High-level Synthesis for Continuous-Flow Microfluidics Considering Hybrid-Scheduling

Mengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann

Component-Oriented High-level Synthesis for Continuous-Flow Microfluidics Considering Hybrid-Scheduling

Details
Discussion Comments: 0
Verification: Authors have not verified information

Dadu: Accelerating Inverse Kinematics for High-DOF Robots

Shiqi Lian, Yinhe Han, Ying Wang, Yungang Bao, Hang Xiao, Xiaowei Li, Ninghui Sun

Dadu: Accelerating Inverse Kinematics for High-DOF Robots

Details
Discussion Comments: 0
Verification: Authors have not verified information

Convergence-Boosted Graph Partitioning using Maximum Spanning Trees for Iterative Solution of Large Linear Circuits

Ya Wang, Wenrui Zhang, Peng Li, Jian Gong

Convergence-Boosted Graph Partitioning using Maximum Spanning Trees for Iterative Solution of Large Linear Circuits

Details
Discussion Comments: 0
Verification: Authors have not verified information

TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks

Ming Cheng, Lixue Xia, Zhenhua Zhu, Yi Cai, Yuan Xie, Yu Wang, Huazhong Yang

TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks

Details
Discussion Comments: 0
Verification: Authors have not verified information

On Characterizing Near-Threshold SRAM Failures in FinFET Technology

Shrikanth Ganapathy, John Kalamatianos, Keith Kasprak, Steven Raasch

On Characterizing Near-Threshold SRAM Failures in FinFET Technology

Details
Discussion Comments: 0
Verification: Authors have not verified information

Formal Techniques for Effective Co-verification of Hardware/Software Co-designs

Rajdeep Mukherjee, Mitra Purandare, Raphael Polig, Daniel Kroening

Formal Techniques for Effective Co-verification of Hardware/Software Co-designs

Details
Discussion Comments: 0
Verification: Authors have not verified information

Towards Full-System Energy-Accuracy Tradeoffs: A Case Study of An Approximate Smart Camera System

Arnab Raha, Vijay Raghunathan

Towards Full-System Energy-Accuracy Tradeoffs: A Case Study of An Approximate Smart Camera System

Details
Discussion Comments: 0
Verification: Authors have not verified information

Detailed Placement for Two-Dimensional Directed Self-Assembly Technology

Zhi-Wen Lin, Yao-Wen Chang

Detailed Placement for Two-Dimensional Directed Self-Assembly Technology

Details
Discussion Comments: 0
Verification: Authors have not verified information

Boosting the Performance of 3D Charge Trap NAND Flash with Asymmetric Feature Process Size Characteristic

Shuo-Han Chen, Yen-Ting Chen, Hsin-Wen Wei, Wei-Kuan Shih

Boosting the Performance of 3D Charge Trap NAND Flash with Asymmetric Feature Process Size Characteristic

Details
Discussion Comments: 0
Verification: Authors have not verified information

Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution

Yanan Lu, Leibo Liu, Yangdong Deng, Jian Weng, Zhaoshi Li, Chenchen Deng, Shaojun Wei

Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution

Details
Discussion Comments: 0
Verification: Authors have not verified information

Exploiting Thread and Data Level Parallelism for Ultimate Parallel SystemC Simulation

Tim Schmidt, Guantao Liu, Rainer Dömer

Exploiting Thread and Data Level Parallelism for Ultimate Parallel SystemC Simulation

Details
Author Comments:
Discussion Comments: 0
Sharing: Research produced artifacts
Verification: Authors have verified information

A Systems Approach to Computing in Beyond CMOS Fabrics: Invited

Ameya Patil, Naresh Shanbhag, Lav R. Varshney, Eric Pop, H.-S. Philip Wong, Subhasish Mitra, Jan M. Rabaey, Jeffrey A. Weldon, Larry T. Pileggi, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young

A Systems Approach to Computing in Beyond CMOS Fabrics: Invited

Details
Discussion Comments: 0
Verification: Authors have not verified information

Low-overhead Aging-aware Resource Management on Embedded GPUs

Haeseung Lee, Muhammad Shafique, Mohammad Abdullah Al Faruque

Low-overhead Aging-aware Resource Management on Embedded GPUs

Details
Discussion Comments: 0
Verification: Authors have not verified information

Closing the Accuracy Gap of Static Performance Analysis of Asynchronous Circuits

Cheng-Yu Shih, Chun-Hong Shih, Jie-Hong R. Jiang

Closing the Accuracy Gap of Static Performance Analysis of Asynchronous Circuits

Details
Discussion Comments: 0
Verification: Authors have not verified information

Bandwidth Optimization Through On-Chip Memory Restructuring for HLS

Jason Cong, Peng Wei, Cody Hao Yu, Peipei Zhou

Bandwidth Optimization Through On-Chip Memory Restructuring for HLS

Details
Discussion Comments: 0
Verification: Authors have not verified information

ObfusCADe: Obfuscating Additive Manufacturing CAD Models Against Counterfeiting: Invited

Nikhil Gupta, Fei Chen, Nektarios Georgios Tsoutsos, Michail Maniatakos

ObfusCADe: Obfuscating Additive Manufacturing CAD Models Against Counterfeiting: Invited

Details
Discussion Comments: 0
Verification: Authors have not verified information

Disturbance Aware Memory Partitioning for Parallel Data Access in STT-RAM

Shouyi Yin, Zhicong Xie, Shaojun Wei

Disturbance Aware Memory Partitioning for Parallel Data Access in STT-RAM

Details
Discussion Comments: 0
Verification: Authors have not verified information

Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs

Xuechao Wei, Cody Hao Yu, Peng Zhang, Youxiang Chen, Yuxin Wang, Han Hu, Yun Liang, Jason Cong

Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs

Details
Author Comments:
Discussion Comments: 0
Sharing: Not able to share produced artifacts
Verification: Authors have verified information

Towards Design and Automation of Hardware-Friendly NOMA Receiver with Iterative Multi-User Detection

Muhammad Adeel Pasha, Momin Uppal, Muhammad Hassan Ahmed, Muhammad Aimal Rehman, Muhammad Awais Bin Altaf

Towards Design and Automation of Hardware-Friendly NOMA Receiver with Iterative Multi-User Detection

Details
Discussion Comments: 0
Verification: Authors have not verified information

A Novel ReRAM-based Main Memory Structure for Optimizing Access Latency and Reliability

Yang Zhang, Dan Feng, Jingning Liu, Wei Tong, Bing Wu, Caihua Fang

A Novel ReRAM-based Main Memory Structure for Optimizing Access Latency and Reliability

Details
Discussion Comments: 0
Verification: Authors have not verified information

Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management

Tianyu Jia, Russ Joseph, Jie Gu

Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management

Details
Discussion Comments: 0
Verification: Authors have not verified information

A-TEAM: Automatic template-based assertion miner

Alessandro Danese, Nicolò Dalla Riva, Graziano Pravadelli

A-TEAM: Automatic template-based assertion miner

Details
Discussion Comments: 0
Verification: Authors have not verified information

LSC: A Large-Scale Consensus-Based Clustering Algorithm for High-Performance FPGAs

Love Singhal, Mahesh A. Iyer, Saurabh N. Adya

LSC: A Large-Scale Consensus-Based Clustering Algorithm for High-Performance FPGAs

Details
Discussion Comments: 0
Verification: Authors have not verified information

Concurrent Pin Access Optimization for Unidirectional Routing

Xiaoqing Xu, Yibo Lin, Vinicius S. Livramento, David Z. Pan

Concurrent Pin Access Optimization for Unidirectional Routing

Details
Discussion Comments: 0
Verification: Authors have not verified information

Optimizing Message Routing and Scheduling in Automotive Mixed-Criticality Time-Triggered Networks

Fedor Smirnov, Michael Glaß, Felix Reimann, Jürgen Teich

Optimizing Message Routing and Scheduling in Automotive Mixed-Criticality Time-Triggered Networks

Details
Discussion Comments: 0
Verification: Authors have not verified information

Optimal Circuits for Parallel Bit Reversal

Ren Chen, Viktor K. Prasanna

Optimal Circuits for Parallel Bit Reversal

Details
Discussion Comments: 0
Verification: Authors have not verified information

Real-Time Multi-Scale Pedestrian Detection for Driver Assistance Systems

Maryam Hemmati, Morteza Biglari-Abhari, Smaïl Niar, Stevan Berber

Real-Time Multi-Scale Pedestrian Detection for Driver Assistance Systems

Details
Discussion Comments: 0
Verification: Authors have not verified information

Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture

Qinghang Zhao, Yongpan Liu, Wenyu Sun, Jiaqing Zhao, Hailong Yao, Xiaojun Guo, Huazhong Yang

Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture

Details
Discussion Comments: 0
Verification: Authors have not verified information

Secure and Reliable XOR Arbiter PUF Design: An Experimental Study based on 1 Trillion Challenge Response Pair Measurements

Chen Zhou, Keshab K. Parhi, Chris H. Kim

Secure and Reliable XOR Arbiter PUF Design: An Experimental Study based on 1 Trillion Challenge Response Pair Measurements

Details
Discussion Comments: 0
Verification: Authors have not verified information

Hardware ODE Solvers using Stochastic Circuits

Siting Liu, Jie Han

Hardware ODE Solvers using Stochastic Circuits

Details
Discussion Comments: 0
Verification: Authors have not verified information

EDiFy: An Execution time Distribution Finder

Boudewijn Braams, Sebastian Altmeyer, Andy D. Pimentel

EDiFy: An Execution time Distribution Finder

Details
Discussion Comments: 0
Verification: Authors have not verified information

A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications

Sebastian Haas, Tobias Seifert, Benedikt Nöthen, Stefan Scholze, Sebastian Höppner, Andreas Dixius, Esther Pérez Adeva, Thomas R. Augustin, Friedrich Pauls, Sadia Moriam, Mattis Hasler, Erik Fischer, Yong Chen, Emil Matús, Georg Ellguth, Stephan Hartmann, Stefan Schiefer, Love Cederström, Dennis Walter, Stephan Henker, Stefan Hänzsche, Johannes Uhlig, Holger Eisenreich, Stefan Weithoffer, Norbert Wehn, René Schüffny, Christian Mayr, Gerhard P. Fettweis

A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications

Details
Discussion Comments: 0
Verification: Authors have not verified information

Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning

Haoyu Yang, Jing Su, Yi Zou, Bei Yu, Evangeline F. Y. Young

Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning

Details
Discussion Comments: 0
Verification: Authors have not verified information

Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond

Jian Kuang, Evangeline F. Y. Young

Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond

Details
Discussion Comments: 0
Verification: Authors have not verified information

A Fast and Power Efficient Architecture to Parallelize LSTM based RNN for Cognitive Intelligence Applications

Peng Ouyang, Shouyi Yin, Shaojun Wei

A Fast and Power Efficient Architecture to Parallelize LSTM based RNN for Cognitive Intelligence Applications

Details
Discussion Comments: 0
Verification: Authors have not verified information

An Architecture for Learning Stream Distributions with Application to RNG Testing

Alric Althoff, Ryan Kastner

An Architecture for Learning Stream Distributions with Application to RNG Testing

Details
Discussion Comments: 0
Verification: Authors have not verified information

Compiler Techniques to Reduce the Synchronization Overhead of GPU Redundant Multithreading

Manish Gupta, Daniel Lowell, John Kalamatianos, Steven Raasch, Vilas Sridharan, Dean M. Tullsen, Rajesh K. Gupta

Compiler Techniques to Reduce the Synchronization Overhead of GPU Redundant Multithreading

Details
Discussion Comments: 0
Verification: Authors have not verified information

LO-FAT: Low-Overhead Control Flow ATtestation in Hardware

Ghada Dessouky, Shaza Zeitouni, Thomas Nyman, Andrew Paverd, Lucas Davi, Patrick Koeberl, N. Asokan, Ahmad-Reza Sadeghi

LO-FAT: Low-Overhead Control Flow ATtestation in Hardware

Details
Discussion Comments: 0
Verification: Authors have not verified information

Accelerator Design for Deep Learning Training: Extended Abstract: Invited

Ankur Agrawal, Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Jinwook Oh, Sunil Shukla, Viji Srinivasan, Swagath Venkataramani, Wei Zhang

Accelerator Design for Deep Learning Training: Extended Abstract: Invited

Details
Discussion Comments: 0
Verification: Authors have not verified information

FFD: A Framework for Fake Flash Detection

Zimu Guo, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte

FFD: A Framework for Fake Flash Detection

Details
Discussion Comments: 0
Verification: Authors have not verified information

A Comprehensive Framework for Synthesizing Stencil Algorithms on FPGAs using OpenCL Model

Shuo Wang, Yun Liang

A Comprehensive Framework for Synthesizing Stencil Algorithms on FPGAs using OpenCL Model

Details
Discussion Comments: 0
Verification: Authors have not verified information

Co-training of Feature Extraction and Classification using Partitioned Convolutional Neural Networks

Wei-Yu Tsai, Jinhang Choi, Tulika Parija, Priyanka Gomatam, Chita R. Das, John Sampson, Vijaykrishnan Narayanan

Co-training of Feature Extraction and Classification using Partitioned Convolutional Neural Networks

Details
Discussion Comments: 0
Verification: Authors have not verified information

Fast and Energy-Efficient Digital Filters for Signal Conditioning in Low-Power Microcontrollers

Carlos Moreno, Sebastian Fischmeister

Fast and Energy-Efficient Digital Filters for Signal Conditioning in Low-Power Microcontrollers

Details
Discussion Comments: 0
Verification: Authors have not verified information

Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design

Gengjie Chen, Jian Kuang, Zhiliang Zeng, Hang Zhang, Evangeline F. Y. Young, Bei Yu

Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design

Details
Discussion Comments: 0
Verification: Authors have not verified information

HyCUBE: A CGRA with Reconfigurable Single-cycle Multi-hop Interconnect

Manupa Karunaratne, Aditi Kulkarni Mohite, Tulika Mitra, Li-Shiuan Peh

HyCUBE: A CGRA with Reconfigurable Single-cycle Multi-hop Interconnect

Details
Discussion Comments: 0
Verification: Authors have not verified information

iClaire: A Fast and General Layout Pattern Classification Algorithm

Wei-Chun Chang, Iris Hui-Ru Jiang, Yen-Ting Yu, Wei-Fang Liu

iClaire: A Fast and General Layout Pattern Classification Algorithm

Details
Discussion Comments: 0
Verification: Authors have not verified information

Network Synthesis for Database Processing Units

Andrea Lottarini, Stephen A. Edwards, Kenneth A. Ross, Martha A. Kim

Network Synthesis for Database Processing Units

Details
Discussion Comments: 0
Verification: Authors have not verified information

Optimizing Memory Efficiency for Convolution Kernels on Kepler GPUs

Xiaoming Chen, Jianxu Chen, Danny Z. Chen, Xiaobo Sharon Hu

Optimizing Memory Efficiency for Convolution Kernels on Kepler GPUs

Details
Discussion Comments: 0
Verification: Authors have not verified information

A Spectral Graph Sparsification Approach to Scalable Vectorless Power Grid Integrity Verification

Zhiqiang Zhao, Zhuo Feng

A Spectral Graph Sparsification Approach to Scalable Vectorless Power Grid Integrity Verification

Details
Discussion Comments: 0
Verification: Authors have not verified information

Secure Information Flow Verification with Mutable Dependent Types

Andrew Ferraiuolo, Weizhe Hua, Andrew C. Myers, G. Edward Suh

Secure Information Flow Verification with Mutable Dependent Types

Details
Discussion Comments: 0
Verification: Authors have not verified information

HALWPE: Hardware-Assisted Light Weight Performance Estimation for GPUs

Kenneth O'Neal, Philip Brisk, Emily Shriver, Michael Kishinevsky

HALWPE: Hardware-Assisted Light Weight Performance Estimation for GPUs

Details
Discussion Comments: 0
Verification: Authors have not verified information

Graph-Based Logic Bit Slicing for Datapath-Aware Placement

Chau-Chin Huang, Bo-Qiao Lin, Hsin-Ying Lee, Yao-Wen Chang, Kuo-Sheng Wu, Jun-Zhi Yang

Graph-Based Logic Bit Slicing for Datapath-Aware Placement

Details
Discussion Comments: 0
Verification: Authors have not verified information

On Quality Trade-off Control for Approximate Computing Using Iterative Training

Chengwen Xu, Xiangyu Wu, Wenqi Yin, Qiang Xu, Naifeng Jing, Xiaoyao Liang, Li Jiang

On Quality Trade-off Control for Approximate Computing Using Iterative Training

Details
Discussion Comments: 0
Verification: Authors have not verified information

Ultra-Efficient Processing In-Memory for Data Intensive Applications

Mohsen Imani, Saransh Gupta, Tajana Rosing

Ultra-Efficient Processing In-Memory for Data Intensive Applications

Details
Discussion Comments: 0
Verification: Authors have not verified information

SmartSwap: High-Performance and User Experience Friendly Swapping in Mobile Systems

Xiao Zhu, Duo Liu, Kan Zhong, Jinting Ren, Tao Li

SmartSwap: High-Performance and User Experience Friendly Swapping in Mobile Systems

Details
Discussion Comments: 0
Verification: Authors have not verified information

A 700fps Optimized Coarse-to-Fine Shape Searching Based Hardware Accelerator for Face Alignment

Qiang Wang, Leibo Liu, Wenping Zhu, Huiyu Mo, Chenchen Deng, Shaojun Wei

A 700fps Optimized Coarse-to-Fine Shape Searching Based Hardware Accelerator for Face Alignment

Details
Discussion Comments: 0
Verification: Authors have not verified information

Cryo-CMOS Electronic Control for Scalable Quantum Computing: Invited

Fabio Sebastiano, Harald Homulle, Bishnu Patra, Rosario M. Incandela, Jeroen P. G. van Dijk, Lin Song, Masoud Babaie, Andrei Vladimirescu, Edoardo Charbon

Cryo-CMOS Electronic Control for Scalable Quantum Computing: Invited

Details
Discussion Comments: 0
Verification: Authors have not verified information

Efficient Bayesian Yield Optimization Approach for Analog and SRAM Circuits

Mengshuo Wang, Fan Yang, Changhao Yan, Xuan Zeng, Xiangdong Hu

Efficient Bayesian Yield Optimization Approach for Analog and SRAM Circuits

Details
Discussion Comments: 0
Verification: Authors have not verified information

Toss-up Wear Leveling: Protecting Phase-Change Memories from Inconsistent Write Patterns

Xian Zhang, Guangyu Sun

Toss-up Wear Leveling: Protecting Phase-Change Memories from Inconsistent Write Patterns

Details
Discussion Comments: 0
Verification: Authors have not verified information

Enabling Write-Reduction Strategy for Journaling File Systems over Byte-addressable NVRAM

Tseng-Yi Chen, Yuan-Hao Chang, Shuo-Han Chen, Chih-Ching Kuo, Ming-Chang Yang, Hsin-Wen Wei, Wei-Kuan Shih

Enabling Write-Reduction Strategy for Journaling File Systems over Byte-addressable NVRAM

Details
Discussion Comments: 0
Verification: Authors have not verified information