| Title: |
Boosting the Performance of 3D Charge Trap NAND Flash with Asymmetric Feature Process Size Characteristic |
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| Authors: |
Shuo-Han Chen |
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National Tsing Hua University, Department of Computer Science
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| Yen-Ting Chen |
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National Tsing Hua University, Department of Computer Science
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| Hsin-Wen Wei |
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Tamkang University, Department of Electrical and Computer Engineering
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| Wei-Kuan Shih |
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National Tsing Hua University, Department of Computer Science
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| Sharing: |
Unknown
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| Verification: |
Authors have
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none
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| DBLP Key: |
conf/dac/ChenCWS17
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