Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture

Article Details
Title:	Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture
Article URLs:	https://doi.org/10.1145/3061639.3062227
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Authors:	Qinghang Zhao	Tsinghua University, Department of Electronic Engineering
	Yongpan Liu	Tsinghua University, Department of Electronic Engineering
	Wenyu Sun	Tsinghua University, Department of Electronic Engineering
	Jiaqing Zhao	Shanghai Jiao Tong University, Department of Electronic Engineering
	Hailong Yao	Tsinghua University, Department of Electronic Engineering
	Xiaojun Guo	Shanghai Jiao Tong University, Department of Electronic Engineering
	Huazhong Yang	Tsinghua University, Department of Electronic Engineering
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DBLP Key:	conf/dac/ZhaoLSZYGY17
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Design Automation Conference, DAC 2017