| Title/Authors | Title | Research Artifacts
[?] A research
artifact is any by-product of a research project that is not
directly included in the published research paper. In Computer
Science research this is often source code and data sets, but
it could also be media, documentation, inputs to proof
assistants, shell-scripts to run experiments, etc.
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Shouyi Yin, Xianqing Yao, Tianyi Lu, Leibo Liu, Shaojun Wei |
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Efficient and accurate analysis of single event transients propagation using SMT-based techniques Ghaith Bany Hamad, Ghaith Kazma, Otmane Aït Mohamed, Yvon Savaria |
Efficient and accurate analysis of single event transients propagation using SMT-based techniques Details |
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Nian-Ze Lee, Hao-Yuan Kuo, Yi-Hsiang Lai, Jie-Hong R. Jiang |
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Efficient synthesis of graph methods: a dynamically scheduled architecture Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Marco Lattuada, Fabrizio Ferrandi |
Efficient synthesis of graph methods: a dynamically scheduled architecture Details |
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Multilevel design understanding: from specification to logic (invited paper) Sandip Ray, Ian G. Harris, Görschwin Fey, Mathias Soeken |
Multilevel design understanding: from specification to logic (invited paper) Details |
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An optimization-theoretic approach for attacking physical unclonable functions Yuntao Liu, Yang Xie, Chongxi Bao, Ankur Srivastava |
An optimization-theoretic approach for attacking physical unclonable functions Details |
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Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne |
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QScale: thermally-efficient QoS management on heterogeneous mobile platforms Onur Sahin, Ayse K. Coskun |
QScale: thermally-efficient QoS management on heterogeneous mobile platforms Details |
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Performance driven routing for modern FPGAs Parivallal Kannan, Satish Sivaswamy |
Performance driven routing for modern FPGAs Details |
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Security engineering of nanostructures and nanomaterials Davood Shahrjerdi, Bayan Nasri, D. Armstrong, Abdullah Alharbi, Ramesh Karri |
Security engineering of nanostructures and nanomaterials Details |
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A flash-based digital circuit design flow Monther Abusultan, Sunil P. Khatri |
A flash-based digital circuit design flow Details |
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MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan |
MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes Details |
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Voltage-based electromigration immortality check for general multi-branch interconnects Zeyu Sun, Ertugrul Demircan, Mehul D. Shroff, Taeyoung Kim, Xin Huang, Sheldon X.-D. Tan |
Voltage-based electromigration immortality check for general multi-branch interconnects Details |
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Making split-fabrication more secure Ping-Lin Yang, Malgorzata Marek-Sadowska |
Making split-fabrication more secure Details |
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A hardware-based technique for efficient implicit information flow tracking Jangseop Shin, Hongce Zhang, Jinyong Lee, Ingoo Heo, Yu-Yuan Chen, Ruby B. Lee, Yunheung Paek |
A hardware-based technique for efficient implicit information flow tracking Details |
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Analysis of production data manipulation attacks in petroleum cyber-physical systems Xiaodao Chen, Yuchen Zhou, Hong Zhou, Chaowei Wan, Qi Zhu, Wenchao Li, Shiyan Hu |
Analysis of production data manipulation attacks in petroleum cyber-physical systems Details |
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Improved flop tray-based design implementation for power reduction Andrew B. Kahng, Jiajia Li, Lutong Wang |
Improved flop tray-based design implementation for power reduction Details |
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Redistribution layer routing for integrated fan-out wafer-level chip-scale packages Bo-Qiao Lin, Ting-Chou Lin, Yao-Wen Chang |
Redistribution layer routing for integrated fan-out wafer-level chip-scale packages Details |
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Szu-Pang Mu, Wen-Hsiang Chang, Mango C.-T. Chao, Yi-Ming Wang, Ming-Tung Chang, Min-Hsiu Tsai |
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Giuseppe Natale, Giulio Stramondo, Pietro Bressana, Riccardo Cattaneo, Donatella Sciuto, Marco D. Santambrogio |
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Autonomous sensor-context learning in dynamic human-centered internet-of-things environments Seyed Ali Rokni, Hassan Ghasemzadeh |
Autonomous sensor-context learning in dynamic human-centered internet-of-things environments Details |
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BoostNoC: power efficient network-on-chip architecture for near threshold computing Chidhambaranathan Rajamanikkam, Rajesh J. S., Koushik Chakraborty, Sanghamitra Roy |
BoostNoC: power efficient network-on-chip architecture for near threshold computing Details |
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Overview of the 2016 CAD contest at ICCAD Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim, Shigetoshi Nakatake |
Overview of the 2016 CAD contest at ICCAD Details |
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Duplex: simultaneous parameter-performance exploration for optimizing analog circuits Seyed Nematollah Ahmadyan, Shobha Vasudevan |
Duplex: simultaneous parameter-performance exploration for optimizing analog circuits Details |
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GPlace: a congestion-aware placement tool for ultrascale FPGAs Ryan Pattison, Ziad Abuowaimer, Shawki Areibi, Gary Gréwal, Anthony Vannelli |
GPlace: a congestion-aware placement tool for ultrascale FPGAs Details |
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Generation and use of statistical timing macro-models considering slew and load variability Debjit Sinha, Vladimir Zolotov, Jin Hu, Sheshashayee K. Raghunathan, Adil Bhanji, Christine M. Casey |
Generation and use of statistical timing macro-models considering slew and load variability Details |
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Xinhai Zhang, Lei Feng, Martin Törngren, De-Jiu Chen |
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Encasing block ciphers to foil key recovery attempts via side channel Giovanni Agosta, Alessandro Barenghi, Gerardo Pelosi, Michele Scandale |
Encasing block ciphers to foil key recovery attempts via side channel Details |
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Reconfigurable in-memory computing with resistive memory crossbar Yue Zha, Jing Li |
Reconfigurable in-memory computing with resistive memory crossbar Details |
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Imprecise security: quality and complexity tradeoffs for hardware information flow tracking Wei Hu, Andrew Becker, Armita Ardeshiricham, Yu Tai, Paolo Ienne, Dejun Mu, Ryan Kastner |
Imprecise security: quality and complexity tradeoffs for hardware information flow tracking Details |
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Hang Zhang, Bei Yu, Evangeline F. Y. Young |
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A novel unified dummy fill insertion framework with SQP-based optimization method Yudong Tao, Changhao Yan, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng |
A novel unified dummy fill insertion framework with SQP-based optimization method Details |
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KCAD: kinetic cyber-attack detection method for cyber-physical additive manufacturing systems Sujit Rokka Chhetri, Arquimedes Canedo, Mohammad Abdullah Al Faruque |
KCAD: kinetic cyber-attack detection method for cyber-physical additive manufacturing systems Details |
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Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing Pai-Yu Chen, Jae-sun Seo, Yu Cao, Shimeng Yu |
Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing Details |
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Security of neuromorphic computing: thwarting learning attacks using memristor's obsolescence effect Chaofei Yang, Beiye Liu, Hai Li, Yiran Chen, Wujie Wen, Mark Barnell, Qing Wu, Jeyavijayan Rajendran |
Security of neuromorphic computing: thwarting learning attacks using memristor's obsolescence effect Details |
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A tensor-based volterra series black-box nonlinear system identification and simulation framework Kim Batselier, Zhongming Chen, Haotian Liu, Ngai Wong |
A tensor-based volterra series black-box nonlinear system identification and simulation framework Details |
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Provably secure camouflaging strategy for IC protection Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, David Z. Pan |
Provably secure camouflaging strategy for IC protection Details |
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Automated error prediction for approximate sequential circuits Amrut Kapare, Hari Cherupalli, John Sartori |
Automated error prediction for approximate sequential circuits Details |
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Control synthesis and delay sensor deployment for efficient ASV designs Chaofan Li, Sachin S. Sapatnekar, Jiang Hu |
Control synthesis and delay sensor deployment for efficient ASV designs Details |
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Lorenzo Ciampolini, Jean-Christophe Lafont, Faress Tissafi Drissi, Jean-Paul Morin, David Turgis, Xavier Jonsson, Cyril Desclèves, Joseph Nguyen |
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Scalable, high-quality, SAT-based multi-layer escape routing Sam Bayless, Holger H. Hoos, Alan J. Hu |
Scalable, high-quality, SAT-based multi-layer escape routing Details |
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The art of semi-formal bug hunting Pradeep Kumar Nalla, Raj Kumar Gajavelly, Jason Baumgartner, Hari Mony, Robert Kanzelman, Alexander Ivrii |
The art of semi-formal bug hunting Details |
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A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel Sicheng Li, Yandan Wang, Wujie Wen, Yu Wang, Yiran Chen, Hai Li |
A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel Details |
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Model-based design of resource-efficient automotive control software Wanli Chang, Debayan Roy, Licong Zhang, Samarjit Chakraborty |
Model-based design of resource-efficient automotive control software Details |
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Delay-optimal technology mapping for in-memory computing using ReRAM devices Debjyoti Bhattacharjee, Anupam Chattopadhyay |
Delay-optimal technology mapping for in-memory computing using ReRAM devices Details |
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Allocation of multi-bit flip-flops in logic synthesis for power optimization Dongyoun Yi, Taewhan Kim |
Allocation of multi-bit flip-flops in logic synthesis for power optimization Details |
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OpenDesign flow database: the infrastructure for VLSI design and design automation research Jinwook Jung, Iris Hui-Ru Jiang, Gi-Joon Nam, Victor N. Kravets, Laleh Behjat, Yih-Lang Li |
OpenDesign flow database: the infrastructure for VLSI design and design automation research Details |
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Malicious LUT: a stealthy FPGA trojan injected and triggered by the design flow Christian Krieg, Clifford Wolf, Axel Jantsch |
Malicious LUT: a stealthy FPGA trojan injected and triggered by the design flow Details |
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Where formal verification can help in functional safety analysis Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann |
Where formal verification can help in functional safety analysis Details |
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Architectural-space exploration of approximate multipliers Semeen Rehman, Walaa El-Harouni, Muhammad Shafique, Akash Kumar, Jörg Henkel |
Architectural-space exploration of approximate multipliers Details |
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Efficient statistical validation of machine learning systems for autonomous driving Weijing Shi, Mohamed Baker Alawieh, Xin Li, Huafeng Yu, Nikos Aréchiga, Nobuyuki Tomatsu |
Efficient statistical validation of machine learning systems for autonomous driving Details |
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Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Sung Kyu Lim |
Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs Details |
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Shuangchen Li, Liu Liu, Peng Gu, Cong Xu, Yuan Xie |
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Resiliency in dynamically power managed designs Liangzhen Lai, Vikas Chandra, Rob Aitken |
Resiliency in dynamically power managed designs Details |
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Design space exploration of drone infrastructure for large-scale delivery services Sangyoung Park, Licong Zhang, Samarjit Chakraborty |
Design space exploration of drone infrastructure for large-scale delivery services Details |
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Testing automotive embedded systems under X-in-the-loop setups Ghizlane Tibba, Christoph Malz, Christoph Stoermer, Natarajan Nagarajan, Licong Zhang, Samarjit Chakraborty |
Testing automotive embedded systems under X-in-the-loop setups Details |
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Formal approaches to design of active cell balancing architectures in battery management systems Sebastian Steinhorst, Martin Lukasiewycz |
Formal approaches to design of active cell balancing architectures in battery management systems Details |
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Dynamic reliability management for near-threshold dark silicon processors Taeyoung Kim, Zeyu Sun, Chase Cook, Jagadeesh Gaddipati, Hai Wang, Hai-Bao Chen, Sheldon X.-D. Tan |
Dynamic reliability management for near-threshold dark silicon processors Details |
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A fast layer elimination approach for power grid reduction Abdul-Amir Yassine, Farid N. Najm |
A fast layer elimination approach for power grid reduction Details |
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Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design Warren Kemmerer, Wei Zuo, Deming Chen |
Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design Details |
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Approximation knob: power capping meets energy efficiency Anil Kanduri, Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Pasi Liljeberg, Axel Jantsch, Nikil D. Dutt, Hannu Tenhunen |
Approximation knob: power capping meets energy efficiency Details |
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SAINT: handling module folding and alignment in fixed-outline floorplans for 3D ICs Jai-Ming Lin, Po-Yang Chiu, Yen-Fu Chang |
SAINT: handling module folding and alignment in fixed-outline floorplans for 3D ICs Details |
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Deepak Kadetotad, Sairam Arunachalam, Chaitali Chakrabarti, Jae-sun Seo |
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Handi Yu, Jun Tao, Changhai Liao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li |
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Error recovery in a micro-electrode-dot-array digital microfluidic biochip? Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Miroslav Pajic, Tsung-Yi Ho, Chen-Yi Lee |
Error recovery in a micro-electrode-dot-array digital microfluidic biochip? Details |
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Energy-efficient and reliable 3D network-on-chip (NoC): architectures and optimization algorithms Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty |
Energy-efficient and reliable 3D network-on-chip (NoC): architectures and optimization algorithms Details |
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Multi-objective design optimization for flexible hybrid electronics Ganapati Bhat, Ujjwal Gupta, Nicholas Tran, Jaehyun Park, Sule Ozev, Ümit Y. Ogras |
Multi-objective design optimization for flexible hybrid electronics Details |
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Compiled symbolic simulation for systemC Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler |
Compiled symbolic simulation for systemC Details |
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Neural networks designing neural networks: multi-objective hyper-parameter optimization Sean C. Smithson, Guang Yang, Warren J. Gross, Brett H. Meyer |
Neural networks designing neural networks: multi-objective hyper-parameter optimization Details |
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Chip editor: leveraging circuit edit for logic obfuscation and trusted fabrication Bicky Shakya, Navid Asadizanjani, Domenic Forte, Mark Mohammad Tehranipoor |
Chip editor: leveraging circuit edit for logic obfuscation and trusted fabrication Details |
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Rasit Onur Topaloglu |
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VCR: simultaneous via-template and cut-template-aware routing for directed self-assembly technology Yu-Hsuan Su, Yao-Wen Chang |
VCR: simultaneous via-template and cut-template-aware routing for directed self-assembly technology Details |
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Lengfei Han, Zhuo Feng |
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OWARU: free space-aware timing-driven incremental placement Jinwook Jung, Gi-Joon Nam, Lakshmi N. Reddy, Iris Hui-Ru Jiang, Youngsoo Shin |
OWARU: free space-aware timing-driven incremental placement Details |
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From biochips to quantum circuits: computer-aided design for emerging technologies Robert Wille, Bing Li, Ulf Schlichtmann, Rolf Drechsler |
From biochips to quantum circuits: computer-aided design for emerging technologies Details |
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LRR-DPUF: learning resilient and reliable digital physical unclonable function Jin Miao, Meng Li, Subhendu Roy, Bei Yu |
LRR-DPUF: learning resilient and reliable digital physical unclonable function Details |
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CamoPerturb: secure IC camouflaging for minterm protection Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran |
CamoPerturb: secure IC camouflaging for minterm protection Details |
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Rudolf Scheifele |
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A new tightly-coupled transient electro-thermal simulation method for power electronics Quan Chen, Wim Schoenmaker |
A new tightly-coupled transient electro-thermal simulation method for power electronics Details |
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On detecting delay anomalies introduced by hardware trojans Dylan Ismari, Jim Plusquellic, Charles Lamech, Swarup Bhunia, Fareena Saqib |
On detecting delay anomalies introduced by hardware trojans Details |
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Bowen Zheng, Chung-Wei Lin, Huafeng Yu, Hengyi Liang, Qi Zhu |
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The architecture value engine: measuring and delivering sustainable SoC improvement Juan Antonio Carballo, Bangqi Xu |
The architecture value engine: measuring and delivering sustainable SoC improvement Details |
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Design of power-efficient approximate multipliers for approximate artificial neural networks Vojtech Mrazek, Syed Shakib Sarwar, Lukás Sekanina, Zdenek Vasícek, Kaushik Roy |
Design of power-efficient approximate multipliers for approximate artificial neural networks Details |
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Grace Li Zhang, Bing Li, Ulf Schlichtmann |
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Multibank memory optimization for parallel data access in multiple data arrays Shouyi Yin, Zhicong Xie, Chenyue Meng, Leibo Liu, Shaojun Wei |
Multibank memory optimization for parallel data access in multiple data arrays Details |
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TASA: toolchain-agnostic static software randomisation for critical real-time systems Leonidas Kosmidis, Roberto Vargas, David Morales, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla |
TASA: toolchain-agnostic static software randomisation for critical real-time systems Details |
Author Comments:
Due to licensing restrictions, TASA is only distributed in binary form upon request.
The hardware platform on which TASA was evaluated can be obtained from http://www.gaisler.com/index.php/products/processors/leon3
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Control-fluidic CoDesign for paper-based digital microfluidic biochips Qin Wang, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li, Ulf Schlichtmann, Yici Cai |
Control-fluidic CoDesign for paper-based digital microfluidic biochips Details |
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Incorporating cut redistribution with mask assignment to enable 1D gridded design Jian Kuang, Evangeline F. Y. Young, Bei Yu |
Incorporating cut redistribution with mask assignment to enable 1D gridded design Details |
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Synthesis of statically analyzable accelerator networks from sequential programs Shaoyi Cheng, John Wawrzynek |
Synthesis of statically analyzable accelerator networks from sequential programs Details |
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IC thermal analyzer for versatile 3-D structures using multigrid preconditioned krylov methods Scott Ladenheim, Yi-Chung Chen, Milan Mihajlovic, Vasilis F. Pavlidis |
IC thermal analyzer for versatile 3-D structures using multigrid preconditioned krylov methods Details |
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A machine learning approach to fab-of-origin attestation Ali Ahmadi, Mohammad-Mahdi Bidmeshki, Amit Nahar, Bob Orr, Michael Pas, Yiorgos Makris |
A machine learning approach to fab-of-origin attestation Details |
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Caffeine: towards uniformed representation and acceleration for deep convolutional neural networks Chen Zhang, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong |
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Scope - quality retaining display rendering workload scaling based on user-smartphone distance Kent W. Nixon, Xiang Chen, Yiran Chen |
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The hype, myths, and realities of testing 3D integrated circuits Ran Wang, Sergej Deutsch, Mukesh Agrawal, Krishnendu Chakrabarty |
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Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration Dylan C. Stow, Itir Akgun, Russell Barnes, Peng Gu, Yuan Xie |
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BugMD: automatic mismatch diagnosis for bug triaging Biruk Mammo, Milind Furia, Valeria Bertacco, Scott A. Mahlke, Daya Shanker Khudia |
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Splitting functions in code management on scratchpad memories Youngbin Kim, Jian Cai, Yooseong Kim, Kyoungwoo Lee, Aviral Shrivastava |
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Chenyuan Zhao, Jialing Li, Yang Yi |
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Sukeshwar Kannan, Mehdi Sadi, Luke England |
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Security and privacy threats to on-chip non-volatile memories and countermeasures Swaroop Ghosh, Mohammad Nasim Imtiaz Khan, Asmit De, Jae-Won Jang |
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Ye Wang, Constantine Caramanis, Michael Orshansky |
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Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits Xunzhao Yin, Ahmedullah Aziz, Joseph Nahas, Suman Datta, Sumeet Kumar Gupta, Michael T. Niemier, Xiaobo Sharon Hu |
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A deterministic approach to stochastic computation Devon Jenson, Marc D. Riedel |
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RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu |
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Exact diagnosis using boolean satisfiability Heinz Riener, Görschwin Fey |
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Adaptive performance prediction for integrated GPUs Ujjwal Gupta, Joseph Campbell, Ümit Y. Ogras, Raid Ayoub, Michael Kishinevsky, Francesco Paterna, Suat Gumussoy |
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ICCAD-2016 CAD contest in large-scale identical fault search Tangent Wei, Luke Lin |
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Measuring progress and value of IC implementation technology Andrew B. Kahng, Hyein Lee, Jiajia Li |
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Critical path isolation for time-to-failure extension and lower voltage operation Yutaka Masuda, Masanori Hashimoto, Takao Onoye |
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Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices Ying Wang, Huawei Li, Xiaowei Li |
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Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip Andrea Peano, Luca Ramini, Marco Gavanelli, Maddalena Nonato, Davide Bertozzi |
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Framework designs to enhance reliable and timely services of disaster management systems Chi-Sheng Shih, Pi-Cheng Hsiu, Yuan-Hao Chang, Tei-Wei Kuo |
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Are proximity attacks a threat to the security of split manufacturing of integrated circuits? Jonathon Magaña, Daohang Shi, Azadeh Davoodi |
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Circuit valorization in the IC design ecosystem José Pineda de Gyvez, Hamed Fatemi, Maarten Vertregt |
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OpenRAM: an open-source memory compiler Matthew R. Guthaus, James E. Stine, Samira Ataei, Brian Chen, Bin Wu, Mehedi Sarwar |
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Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools Kyungwook Chang, Saurabh Sinha, Brian Cline, Raney Southerland, Michael Doherty, Greg Yeric, Sung Kyu Lim |
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Fast physics-based electromigration checking for on-die power grids Sandeep Chatterjee, Valeriy Sukharev, Farid N. Najm |
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Arbitrary streaming permutations with minimum memory and latency Thaddeus Koehn, Peter M. Athanas |
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Interconnect-aware device targeting from PPA perspective Mustafa Badaroglu, Jeff Xu |
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Detailed placement for modern FPGAs using 2D dynamic programming Shounak Dhar, Saurabh N. Adya, Love Singhal, Mahesh A. Iyer, David Z. Pan |
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Properties first? a new design methodology for hardware, and its perspectives in safety analysis Joakim Urdahl, Shrinidhi Udupi, Tobias Ludwig, Dominik Stoffel, Wolfgang Kunz |
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DSA-compliant routing for two-dimensional patterns using block copolymer lithography Yu-Hsuan Su, Yao-Wen Chang |
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ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY Linuo Xue, Yuanqing Cheng, Jianlei Yang, Peiyuan Wang, Yuan Xie |
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ICCAD-2016 CAD contest in non-exact projective NPNP boolean matching and benchmark suite Chi-An (Rocky) Wu, Chih-Jen (Jacky) Hsu, Kei-Yong Khoo |
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Energy-efficient fault tolerance approach for internet of things applications Teng Xu, Miodrag Potkonjak |
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Zhong Guan, Malgorzata Marek-Sadowska |
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Approximation-aware rewriting of AIGs for error tolerant applications Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler |
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