ACM International Conference on Computer-Aided Design, ICCAD 2016


Title/Authors Title Research Artifacts
[?] A research artifact is any by-product of a research project that is not directly included in the published research paper. In Computer Science research this is often source code and data sets, but it could also be media, documentation, inputs to proof assistants, shell-scripts to run experiments, etc.
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Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory

Shouyi Yin, Xianqing Yao, Tianyi Lu, Leibo Liu, Shaojun Wei

Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory

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Efficient and accurate analysis of single event transients propagation using SMT-based techniques

Ghaith Bany Hamad, Ghaith Kazma, Otmane Aït Mohamed, Yvon Savaria

Efficient and accurate analysis of single event transients propagation using SMT-based techniques

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Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits

Nian-Ze Lee, Hao-Yuan Kuo, Yi-Hsiang Lai, Jie-Hong R. Jiang

Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits

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Efficient synthesis of graph methods: a dynamically scheduled architecture

Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Marco Lattuada, Fabrizio Ferrandi

Efficient synthesis of graph methods: a dynamically scheduled architecture

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Multilevel design understanding: from specification to logic (invited paper)

Sandip Ray, Ian G. Harris, Görschwin Fey, Mathias Soeken

Multilevel design understanding: from specification to logic (invited paper)

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An optimization-theoretic approach for attacking physical unclonable functions

Yuntao Liu, Yang Xie, Chongxi Bao, Ankur Srivastava

An optimization-theoretic approach for attacking physical unclonable functions

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Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications

Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne

Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications

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QScale: thermally-efficient QoS management on heterogeneous mobile platforms

Onur Sahin, Ayse Kivilcim Coskun

QScale: thermally-efficient QoS management on heterogeneous mobile platforms

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Performance driven routing for modern FPGAs

Parivallal Kannan, Satish Sivaswamy

Performance driven routing for modern FPGAs

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Security engineering of nanostructures and nanomaterials

Davood Shahrjerdi, Bayan Nasri, D. Armstrong, Abdullah Alharbi, Ramesh Karri

Security engineering of nanostructures and nanomaterials

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A flash-based digital circuit design flow

Monther Abusultan, Sunil P. Khatri

A flash-based digital circuit design flow

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MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes

Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan

MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes

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Voltage-based electromigration immortality check for general multi-branch interconnects

Zeyu Sun, Ertugrul Demircan, Mehul D. Shrof, Taeyoung Kim, Xin Huang, Sheldon X.-D. Tan

Voltage-based electromigration immortality check for general multi-branch interconnects

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Making split-fabrication more secure

Ping-Lin Yang, Malgorzata Marek-Sadowska

Making split-fabrication more secure

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A hardware-based technique for efficient implicit information flow tracking

Jangseop Shin, Hongce Zhang, Jinyong Lee, Ingoo Heo, Yu-Yuan Chen, Ruby B. Lee, Yunheung Paek

A hardware-based technique for efficient implicit information flow tracking

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Analysis of production data manipulation attacks in petroleum cyber-physical systems

Xiaodao Chen, Yuchen Zhou, Hong Zhou, Chaowei Wan, Qi Zhu, Wenchao Li, Shiyan Hu

Analysis of production data manipulation attacks in petroleum cyber-physical systems

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Improved flop tray-based design implementation for power reduction

Andrew B. Kahng, Jiajia Li, Lutong Wang

Improved flop tray-based design implementation for power reduction

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Redistribution layer routing for integrated fan-out wafer-level chip-scale packages

Bo-Qiao Lin, Ting-Chou Lin, Yao-Wen Chang

Redistribution layer routing for integrated fan-out wafer-level chip-scale packages

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Statistical methodology to identify optimal placement of on-chip process monitors for predicting fmax

Szu-Pang Mu, Wen-Hsiang Chang, Mango C.-T. Chao, Yi-Ming Wang, Ming-Tung Chang, Min-Hsiu Tsai

Statistical methodology to identify optimal placement of on-chip process monitors for predicting fmax

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A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops

Giuseppe Natale, Giulio Stramondo, Pietro Bressana, Riccardo Cattaneo, Donatella Sciuto, Marco D. Santambrogio

A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops

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Autonomous sensor-context learning in dynamic human-centered internet-of-things environments

Seyed Ali Rokni, Hassan Ghasemzadeh

Autonomous sensor-context learning in dynamic human-centered internet-of-things environments

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BoostNoC: power efficient network-on-chip architecture for near threshold computing

Chidhambaranathan Rajamanikkam, Rajesh J. S., Koushik Chakraborty, Sanghamitra Roy

BoostNoC: power efficient network-on-chip architecture for near threshold computing

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Overview of the 2016 CAD contest at ICCAD

Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim, Shigetoshi Nakatake

Overview of the 2016 CAD contest at ICCAD

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Duplex: simultaneous parameter-performance exploration for optimizing analog circuits

Seyed Nematollah Ahmadyan, Shobha Vasudevan

Duplex: simultaneous parameter-performance exploration for optimizing analog circuits

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GPlace: a congestion-aware placement tool for ultrascale FPGAs

Ryan Pattison, Ziad Abuowaimer, Shawki Areibi, Gary Gréwal, Anthony Vannelli

GPlace: a congestion-aware placement tool for ultrascale FPGAs

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Generation and use of statistical timing macro-models considering slew and load variability

Debjit Sinha, Vladimir Zolotov, Jin Hu, Sheshashayee K. Raghunathan, Adil Bhanji, Christine M. Casey

Generation and use of statistical timing macro-models considering slew and load variability

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Formulating customized specifications for resource allocation problem of distributed embedded systems

Xinhai Zhang, Lei Feng, Martin Törngren, De-Jiu Chen

Formulating customized specifications for resource allocation problem of distributed embedded systems

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Encasing block ciphers to foil key recovery attempts via side channel

Giovanni Agosta, Alessandro Barenghi, Gerardo Pelosi, Michele Scandale

Encasing block ciphers to foil key recovery attempts via side channel

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Reconfigurable in-memory computing with resistive memory crossbar

Yue Zha, Jing Li

Reconfigurable in-memory computing with resistive memory crossbar

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Imprecise security: quality and complexity tradeoffs for hardware information flow tracking

Wei Hu, Andrew Becker, Armita Ardeshiricham, Yu Tai, Paolo Ienne, Dejun Mu, Ryan Kastner

Imprecise security: quality and complexity tradeoffs for hardware information flow tracking

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Enabling online learning in lithography hotspot detection with information-theoretic feature optimization

Hang Zhang, Bei Yu, Evangeline F. Y. Young

Enabling online learning in lithography hotspot detection with information-theoretic feature optimization

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A novel unified dummy fill insertion framework with SQP-based optimization method

Yudong Tao, Changhao Yan, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng

A novel unified dummy fill insertion framework with SQP-based optimization method

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KCAD: kinetic cyber-attack detection method for cyber-physical additive manufacturing systems

Sujit Rokka Chhetri, Arquimedes Canedo, Mohammad Abdullah Al Faruque

KCAD: kinetic cyber-attack detection method for cyber-physical additive manufacturing systems

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Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing

Pai-Yu Chen, Jae-sun Seo, Yu Cao, Shimeng Yu

Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing

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Security of neuromorphic computing: thwarting learning attacks using memristor's obsolescence effect

Chaofei Yang, Beiye Liu, Hai Li, Yiran Chen, Wujie Wen, Mark Barnell, Qing Wu, Jeyavijayan Rajendran

Security of neuromorphic computing: thwarting learning attacks using memristor's obsolescence effect

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A tensor-based volterra series black-box nonlinear system identification and simulation framework

Kim Batselier, Zhongming Chen, Haotian Liu, Ngai Wong

A tensor-based volterra series black-box nonlinear system identification and simulation framework

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Provably secure camouflaging strategy for IC protection

Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, David Z. Pan

Provably secure camouflaging strategy for IC protection

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Automated error prediction for approximate sequential circuits

Amrut Kapare, Hari Cherupalli, John Sartori

Automated error prediction for approximate sequential circuits

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Control synthesis and delay sensor deployment for efficient ASV designs

Chaofan Li, Sachin S. Sapatnekar, Jiang Hu

Control synthesis and delay sensor deployment for efficient ASV designs

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Efficient yield estimation through generalized importance sampling with application to NBL-assisted SRAM bitcells

Lorenzo Ciampolini, Jean-Christophe Lafont, Faress Tissafi Drissi, Jean-Paul Morin, David Turgis, Xavier Jonsson, Cyril Desclèves, Joseph Nguyen

Efficient yield estimation through generalized importance sampling with application to NBL-assisted SRAM bitcells

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Scalable, high-quality, SAT-based multi-layer escape routing

Sam Bayless, Holger H. Hoos, Alan J. Hu

Scalable, high-quality, SAT-based multi-layer escape routing

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The art of semi-formal bug hunting

Pradeep Kumar Nalla, Raj Kumar Gajavelly, Jason Baumgartner, Hari Mony, Robert Kanzelman, Alexander Ivrii

The art of semi-formal bug hunting

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A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel

Sicheng Li, Yandan Wang, Wujie Wen, Yu Wang, Yiran Chen, Hai Li

A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel

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Model-based design of resource-efficient automotive control software

Wanli Chang, Debayan Roy, Licong Zhang, Samarjit Chakraborty

Model-based design of resource-efficient automotive control software

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Delay-optimal technology mapping for in-memory computing using ReRAM devices

Debjyoti Bhattacharjee, Anupam Chattopadhyay

Delay-optimal technology mapping for in-memory computing using ReRAM devices

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Allocation of multi-bit flip-flops in logic synthesis for power optimization

Dongyoun Yi, Taewhan Kim

Allocation of multi-bit flip-flops in logic synthesis for power optimization

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OpenDesign flow database: the infrastructure for VLSI design and design automation research

Jinwook Jung, Iris Hui-Ru Jiang, Gi-Joon Nam, Victor N. Kravets, Laleh Behjat, Yih-Lang Li

OpenDesign flow database: the infrastructure for VLSI design and design automation research

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Malicious LUT: a stealthy FPGA trojan injected and triggered by the design flow

Christian Krieg, Clifford Wolf, Axel Jantsch

Malicious LUT: a stealthy FPGA trojan injected and triggered by the design flow

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Where formal verification can help in functional safety analysis

Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann

Where formal verification can help in functional safety analysis

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Architectural-space exploration of approximate multipliers

Semeen Rehman, Walaa El-Harouni, Muhammad Shafique, Akash Kumar, Jörg Henkel

Architectural-space exploration of approximate multipliers

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Efficient statistical validation of machine learning systems for autonomous driving

Weijing Shi, Mohamed Baker Alawieh, Xin Li, Huafeng Yu, Nikos Arechiga, Nobuyuki Tomatsu

Efficient statistical validation of machine learning systems for autonomous driving

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Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs

Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Sung Kyu Lim

Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs

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NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory

Shuangchen Li, Liu Liu, Peng Gu, Cong Xu, Yuan Xie

NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory

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Resiliency in dynamically power managed designs

Liangzhen Lai, Vikas Chandra, Rob Aitken

Resiliency in dynamically power managed designs

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Design space exploration of drone infrastructure for large-scale delivery services

Sangyoung Park, Licong Zhang, Samarjit Chakraborty

Design space exploration of drone infrastructure for large-scale delivery services

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Testing automotive embedded systems under X-in-the-loop setups

Ghizlane Tibba, Christoph Malz, Christoph Stoermer, Natarajan Nagarajan, Licong Zhang, Samarjit Chakraborty

Testing automotive embedded systems under X-in-the-loop setups

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Formal approaches to design of active cell balancing architectures in battery management systems

Sebastian Steinhorst, Martin Lukasiewycz

Formal approaches to design of active cell balancing architectures in battery management systems

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Dynamic reliability management for near-threshold dark silicon processors

Taeyoung Kim, Zeyu Sun, Chase Cook, Jagadeesh Gaddipati, Hai Wang, Hai-Bao Chen, Sheldon X.-D. Tan

Dynamic reliability management for near-threshold dark silicon processors

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A fast layer elimination approach for power grid reduction

Abdul-Amir Yassine, Farid N. Najm

A fast layer elimination approach for power grid reduction

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Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design

Warren Kemmerer, Wei Zuo, Deming Chen

Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design

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Approximation knob: power capping meets energy efficiency

Anil Kanduri, Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Pasi Liljeberg, Axel Jantsch, Nikil D. Dutt, Hannu Tenhunen

Approximation knob: power capping meets energy efficiency

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SAINT: handling module folding and alignment in fixed-outline floorplans for 3D ICs

Jai-Ming Lin, Po-Yang Chiu, Yen-Fu Chang

SAINT: handling module folding and alignment in fixed-outline floorplans for 3D ICs

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Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications

Deepak Kadetotad, Sairam Arunachalam, Chaitali Chakrabarti, Jae-sun Seo

Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications

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Efficient statistical analysis for correlated rare failure events via asymptotic probability approximation

Handi Yu, Jun Tao, Changhai Liao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li

Efficient statistical analysis for correlated rare failure events via asymptotic probability approximation

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Error recovery in a micro-electrode-dot-array digital microfluidic biochip?

Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Miroslav Pajic, Tsung-Yi Ho, Chen-Yi Lee

Error recovery in a micro-electrode-dot-array digital microfluidic biochip?

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Energy-efficient and reliable 3D network-on-chip (NoC): architectures and optimization algorithms

Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty

Energy-efficient and reliable 3D network-on-chip (NoC): architectures and optimization algorithms

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Multi-objective design optimization for flexible hybrid electronics

Ganapati Bhat, Ujjwal Gupta, Nicholas Tran, Jaehyun Park, Sule Ozev, Ümit Y. Ogras

Multi-objective design optimization for flexible hybrid electronics

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Compiled symbolic simulation for systemC

Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler

Compiled symbolic simulation for systemC

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Neural networks designing neural networks: multi-objective hyper-parameter optimization

Sean C. Smithson, Guang Yang, Warren J. Gross, Brett H. Meyer

Neural networks designing neural networks: multi-objective hyper-parameter optimization

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Chip editor: leveraging circuit edit for logic obfuscation and trusted fabrication

Bicky Shakya, Navid Asadizanjani, Domenic Forte, Mark Mohammad Tehranipoor

Chip editor: leveraging circuit edit for logic obfuscation and trusted fabrication

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ICCAD-2016 CAD contest in pattern classification for integrated circuit design space analysis and benchmark suite

Rasit Onur Topaloglu

ICCAD-2016 CAD contest in pattern classification for integrated circuit design space analysis and benchmark suite

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VCR: simultaneous via-template and cut-template-aware routing for directed self-assembly technology

Yu-Hsuan Su, Yao-Wen Chang

VCR: simultaneous via-template and cut-template-aware routing for directed self-assembly technology

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TinySPICE plus: scaling up statistical SPICE simulations on GPU leveraging shared-memory based sparse matrix solution techniques

Lengfei Han, Zhuo Feng

TinySPICE plus: scaling up statistical SPICE simulations on GPU leveraging shared-memory based sparse matrix solution techniques

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OWARU: free space-aware timing-driven incremental placement

Jinwook Jung, Gi-Joon Nam, Lakshmi Reddy, Iris Hui-Ru Jiang, Youngsoo Shin

OWARU: free space-aware timing-driven incremental placement

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From biochips to quantum circuits: computer-aided design for emerging technologies

Robert Wille, Bing Li, Ulf Schlichtmann, Rolf Drechsler

From biochips to quantum circuits: computer-aided design for emerging technologies

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LRR-DPUF: learning resilient and reliable digital physical unclonable function

Jin Miao, Meng Li, Subhendu Roy, Bei Yu

LRR-DPUF: learning resilient and reliable digital physical unclonable function

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CamoPerturb: secure IC camouflaging for minterm protection

Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran

CamoPerturb: secure IC camouflaging for minterm protection

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RC-aware global routing

Rudolf Scheifele

RC-aware global routing

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A new tightly-coupled transient electro-thermal simulation method for power electronics

Quan Chen, Wim Schoenmaker

A new tightly-coupled transient electro-thermal simulation method for power electronics

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On detecting delay anomalies introduced by hardware trojans

Dylan Ismari, Jim Plusquellic, Charles Lamech, Swarup Bhunia, Fareena Saqib

On detecting delay anomalies introduced by hardware trojans

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CONVINCE: a cross-layer modeling, exploration and validation framework for next-generation connected vehicles

Bowen Zheng, Chung-Wei Lin, Huafeng Yu, Hengyi Liang, Qi Zhu

CONVINCE: a cross-layer modeling, exploration and validation framework for next-generation connected vehicles

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The architecture value engine: measuring and delivering sustainable SoC improvement

Juan Antonio Carballo, Bangqi Xu

The architecture value engine: measuring and delivering sustainable SoC improvement

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Design of power-efficient approximate multipliers for approximate artificial neural networks

Vojtech Mrazek, Syed Shakib Sarwar, Lukás Sekanina, Zdenek Vasícek, Kaushik Roy

Design of power-efficient approximate multipliers for approximate artificial neural networks

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PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency using a piecewise model

Grace Li Zhang, Bing Li, Ulf Schlichtmann

PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency using a piecewise model

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Multibank memory optimization for parallel data access in multiple data arrays

Shouyi Yin, Zhicong Xie, Chenyue Meng, Leibo Liu, Shaojun Wei

Multibank memory optimization for parallel data access in multiple data arrays

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TASA: toolchain-agnostic static software randomisation for critical real-time systems

Leonidas Kosmidis, Roberto Vargas, David Morales, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla

TASA: toolchain-agnostic static software randomisation for critical real-time systems

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Author Comments: Due to licensing restrictions, TASA is only distributed in binary form upon request. The hardware platform on which TASA was evaluated can be obtained from http://www.gaisler.com/index.php/products/processors/leon3
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Control-fluidic CoDesign for paper-based digital microfluidic biochips

Qin Wang, Zeyan Li, Haena Cheong, Oh-Sun Kwon, Hailong Yao, Tsung-Yi Ho, Kwanwoo Shin, Bing Li, Ulf Schlichtmann, Yici Cai

Control-fluidic CoDesign for paper-based digital microfluidic biochips

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Incorporating cut redistribution with mask assignment to enable 1D gridded design

Jian Kuang, Evangeline F. Y. Young, Bei Yu

Incorporating cut redistribution with mask assignment to enable 1D gridded design

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Synthesis of statically analyzable accelerator networks from sequential programs

Shaoyi Cheng, John Wawrzynek

Synthesis of statically analyzable accelerator networks from sequential programs

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IC thermal analyzer for versatile 3-D structures using multigrid preconditioned krylov methods

Scott Ladenheim, Yi-Chung Chen, Milan Mihajlovic, Vasilis F. Pavlidis

IC thermal analyzer for versatile 3-D structures using multigrid preconditioned krylov methods

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A machine learning approach to fab-of-origin attestation

Ali Ahmadi, Mohammad-Mahdi Bidmeshki, Amit Nahar, Bob Orr, Michael Pas, Yiorgos Makris

A machine learning approach to fab-of-origin attestation

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A cross-layer approach for resiliency and energy efficiency in near threshold computing

Mohammad Saber Golanbari, Anteneh Gebregiorgis, Fabian Oboril, Saman Kiamehr, Mehdi Baradaran Tahoori

A cross-layer approach for resiliency and energy efficiency in near threshold computing

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Caffeine: towards uniformed representation and acceleration for deep convolutional neural networks

Chen Zhang, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong

Caffeine: towards uniformed representation and acceleration for deep convolutional neural networks

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Scope - quality retaining display rendering workload scaling based on user-smartphone distance

Kent W. Nixon, Xiang Chen, Yiran Chen

Scope - quality retaining display rendering workload scaling based on user-smartphone distance

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The hype, myths, and realities of testing 3D integrated circuits

Ran Wang, Sergej Deutsch, Mukesh Agrawal, Krishnendu Chakrabarty

The hype, myths, and realities of testing 3D integrated circuits

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Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration

Dylan Stow, Itir Akgun, Russell Barnes, Peng Gu, Yuan Xie

Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration

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BugMD: automatic mismatch diagnosis for bug triaging

Biruk Mammo, Milind Furia, Valeria Bertacco, Scott A. Mahlke, Daya Shanker Khudia

BugMD: automatic mismatch diagnosis for bug triaging

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Exploring aging deceleration in FinFET-based multi-core systems

Ermao Cai, Dimitrios Stamoulis, Diana Marculescu

Exploring aging deceleration in FinFET-based multi-core systems

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Splitting functions in code management on scratchpad memories

Youngbin Kim, Jian Cai, Yooseong Kim, Kyoungwoo Lee, Aviral Shrivastava

Splitting functions in code management on scratchpad memories

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Making neural encoding robust and energy efficient: an advanced analog temporal encoder for brain-inspired computing systems

Chenyuan Zhao, Jialing Li, Yang Yi

Making neural encoding robust and energy efficient: an advanced analog temporal encoder for brain-inspired computing systems

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UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing

Wuxi Li, Shounak Dhar, David Z. Pan

UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing

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Power delivery in 3D packages: current crowding effects, dynamic IR drop and compensation network using sensors (invited paper)

Sukeshwar Kannan, Mehdi Sadi, Luke England

Power delivery in 3D packages: current crowding effects, dynamic IR drop and compensation network using sensors (invited paper)

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Security and privacy threats to on-chip non-volatile memories and countermeasures

Swaroop Ghosh, Mohammad Nasim Imtiaz Khan, Asmit De, Jae-Won Jang

Security and privacy threats to on-chip non-volatile memories and countermeasures

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Exploiting randomness in sketching for efficient hardware implementation of machine learning applications

Ye Wang, Constantine Caramanis, Michael Orshansky

Exploiting randomness in sketching for efficient hardware implementation of machine learning applications

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Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits

Xunzhao Yin, Ahmedullah Aziz, Joseph Nahas, Suman Datta, Sumeet Kumar Gupta, Michael T. Niemier, Xiaobo Sharon Hu

Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits

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A deterministic approach to stochastic computation

Devon Jenson, Marc Riedel

A deterministic approach to stochastic computation

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RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs

Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu

RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs

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Exact diagnosis using boolean satisfiability

Heinz Riener, Görschwin Fey

Exact diagnosis using boolean satisfiability

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Privacy protection via appliance scheduling in smart homes

Jie Wu, Jinglan Liu, Xiaobo Sharon Hu, Yiyu Shi

Privacy protection via appliance scheduling in smart homes

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Adaptive performance prediction for integrated GPUs

Ujjwal Gupta, Joseph Campbell, Ümit Y. Ogras, Raid Ayoub, Michael Kishinevsky, Francesco Paterna, Suat Gumussoy

Adaptive performance prediction for integrated GPUs

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ICCAD-2016 CAD contest in large-scale identical fault search

Tangent Wei, Luke Lin

ICCAD-2016 CAD contest in large-scale identical fault search

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Measuring progress and value of IC implementation technology

Andrew B. Kahng, Hyein Lee, Jiajia Li

Measuring progress and value of IC implementation technology

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Critical path isolation for time-to-failure extension and lower voltage operation

Yutaka Masuda, Masanori Hashimoto, Takao Onoye

Critical path isolation for time-to-failure extension and lower voltage operation

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Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices

Ying Wang, Huawei Li, Xiaowei Li

Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices

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Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip

Andrea Peano, Luca Ramini, Marco Gavanelli, Maddalena Nonato, Davide Bertozzi

Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip

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Security challenges in smart surveillance systems and the solutions based on emerging nano-devices

Chaofei Yang, Chunpeng Wu, Hai Li, Yiran Chen, Mark Barnell, Qing Wu

Security challenges in smart surveillance systems and the solutions based on emerging nano-devices

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Framework designs to enhance reliable and timely services of disaster management systems

Chi-Sheng Shih, Pi-Cheng Hsiu, Yuan-Hao Chang, Tei-Wei Kuo

Framework designs to enhance reliable and timely services of disaster management systems

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How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node?

Bon Woong Ku, Peter Debacker, Dragomir Milojevic, Praveen Raghavan, Sung Kyu Lim

How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node?

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Are proximity attacks a threat to the security of split manufacturing of integrated circuits?

Jonathon Magaña, Daohang Shi, Azadeh Davoodi

Are proximity attacks a threat to the security of split manufacturing of integrated circuits?

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Circuit valorization in the IC design ecosystem

José Pineda de Gyvez, Hamed Fatemi, Maarten Vertregt

Circuit valorization in the IC design ecosystem

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OpenRAM: an open-source memory compiler

Matthew R. Guthaus, James E. Stine, Samira Ataei, Brian Chen, Bin Wu, Mehedi Sarwar

OpenRAM: an open-source memory compiler

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Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools

Kyungwook Chang, Saurabh Sinha, Brian Cline, Raney Southerland, Michael Doherty, Greg Yeric, Sung Kyu Lim

Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools

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Fast physics-based electromigration checking for on-die power grids

Sandeep Chatterjee, Valeriy Sukharev, Farid N. Najm

Fast physics-based electromigration checking for on-die power grids

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Arbitrary streaming permutations with minimum memory and latency

Thaddeus Koehn, Peter M. Athanas

Arbitrary streaming permutations with minimum memory and latency

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Interconnect-aware device targeting from PPA perspective

Mustafa Badaroglu, Jeff Xu

Interconnect-aware device targeting from PPA perspective

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Detailed placement for modern FPGAs using 2D dynamic programming

Shounak Dhar, Saurabh N. Adya, Love Singhal, Mahesh A. Iyer, David Z. Pan

Detailed placement for modern FPGAs using 2D dynamic programming

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Properties first? a new design methodology for hardware, and its perspectives in safety analysis

Joakim Urdahl, Shrinidhi Udupi, Tobias Ludwig, Dominik Stoffel, Wolfgang Kunz

Properties first? a new design methodology for hardware, and its perspectives in safety analysis

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DSA-compliant routing for two-dimensional patterns using block copolymer lithography

Yu-Hsuan Su, Yao-Wen Chang

DSA-compliant routing for two-dimensional patterns using block copolymer lithography

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ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY

Linuo Xue, Yuanqing Cheng, Jianlei Yang, Peiyuan Wang, Yuan Xie

ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY

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ICCAD-2016 CAD contest in non-exact projective NPNP boolean matching and benchmark suite

Chi-An (Rocky) Wu, Chih-Jen (Jacky) Hsu, Kei-Yong Khoo

ICCAD-2016 CAD contest in non-exact projective NPNP boolean matching and benchmark suite

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Energy-efficient fault tolerance approach for internet of things applications

Teng Xu, Miodrag Potkonjak

Energy-efficient fault tolerance approach for internet of things applications

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An efficient and accurate algorithm for computing RC current response with applications to EM reliability evaluation

Zhong Guan, Malgorzata Marek-Sadowska

An efficient and accurate algorithm for computing RC current response with applications to EM reliability evaluation

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Approximation-aware rewriting of AIGs for error tolerant applications

Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler

Approximation-aware rewriting of AIGs for error tolerant applications

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