Design Automation Conference, DAC 2016


Title/Authors Title Research Artifacts
[?] A research artifact is any by-product of a research project that is not directly included in the published research paper. In Computer Science research this is often source code and data sets, but it could also be media, documentation, inputs to proof assistants, shell-scripts to run experiments, etc.
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Leveraging FDSOI through body bias domain partitioning and bias search

Johannes Maximilian Kühn, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel

Leveraging FDSOI through body bias domain partitioning and bias search

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Invited - Wireless sensor nodes for environmental monitoring in internet of things

Ting-Chou Lu, Li-Ren Huang, Yu Lee, Kun-Ju Tsai, Yu-Te Liao, Nai-Chen Daniel Cheng, Yuan-Hua Chu, Yi-Hsing Tsai, Fang-Chu Chen, Tzi-cker Chiueh

Invited - Wireless sensor nodes for environmental monitoring in internet of things

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Nonvolatile memory design based on ferroelectric FETs

Sumitha George, Kaisheng Ma, Ahmedullah Aziz, Xueqing Li, Asif Khan, Sayeef Salahuddin, Meng-Fan Chang, Suman Datta, John Sampson, Sumeet Kumar Gupta, Vijaykrishnan Narayanan

Nonvolatile memory design based on ferroelectric FETs

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Reducing serial I/O power in error-tolerant applications by efficient lossy encoding

Phillip Stanley-Marbell, Martin C. Rinard

Reducing serial I/O power in error-tolerant applications by efficient lossy encoding

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Enabling sub-blocks erase management to boost the performance of 3D NAND flash memory

Tseng-Yi Chen, Yuan-Hao Chang, Chien-Chung Ho, Shuo-Han Chen

Enabling sub-blocks erase management to boost the performance of 3D NAND flash memory

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Perform-ML: performance optimized machine learning by platform and content aware customization

Azalia Mirhoseini, Bita Darvish Rouhani, Ebrahim M. Songhori, Farinaz Koushanfar

Perform-ML: performance optimized machine learning by platform and content aware customization

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Designing approximate circuits using clock overgating

Younghoon Kim, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan

Designing approximate circuits using clock overgating

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Invited - Energy harvesting and transient computing: a paradigm shift for embedded systems?

Geoff V. Merrett

Invited - Energy harvesting and transient computing: a paradigm shift for embedded systems?

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An expected hypervolume improvement algorithm for architectural exploration of embedded processors

Hongwei Wang, Jinglin Shi, Ziyuan Zhu

An expected hypervolume improvement algorithm for architectural exploration of embedded processors

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Dot-product engine for neuromorphic computing: programming 1T1M crossbar to accelerate matrix-vector multiplication

Miao Hu, John Paul Strachan, Zhiyong Li, Emmanuelle M. Grafals, Noraica Davila, Catherine Graves, Sity Lam, Ning Ge, Jianhua Joshua Yang, R. Stanley Williams

Dot-product engine for neuromorphic computing: programming 1T1M crossbar to accelerate matrix-vector multiplication

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Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks

Kyounghoon Kim, Jungki Kim, Joonsang Yu, Jungwoo Seo, Jongeun Lee, Kiyoung Choi

Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks

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Invited - Cooperation or competition?: coexistence of safety and security in next-generation ethernet-based automotive networks

Chung-Wei Lin, Huafeng Yu

Invited - Cooperation or competition?: coexistence of safety and security in next-generation ethernet-based automotive networks

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Quest for high-performance bufferless NoCs with single-cycle express paths and self-learning throttling

Bhavya K. Daya, Li-Shiuan Peh, Anantha P. Chandrakasan

Quest for high-performance bufferless NoCs with single-cycle express paths and self-learning throttling

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Invited - Heterogeneous datacenters: options and opportunities

Jason Cong, Muhuan Huang, Di Wu, Cody Hao Yu

Invited - Heterogeneous datacenters: options and opportunities

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A low-cost conflict-free NoC for GPGPUs

Xia Zhao, Sheng Ma, Yuxi Liu, Lieven Eeckhout, Zhiying Wang

A low-cost conflict-free NoC for GPGPUs

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A Monte Carlo simulation flow for SEU analysis of sequential circuits

Meng Li, Ye Wang, Michael Orshansky

A Monte Carlo simulation flow for SEU analysis of sequential circuits

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A high-resolution side-channel attack on last-level cache

Mehmet Kayaalp, Nael B. Abu-Ghazaleh, Dmitry V. Ponomarev, Aamer Jaleel

A high-resolution side-channel attack on last-level cache

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SecDCP: secure dynamic cache partitioning for efficient timing channel protection

Yao Wang, Andrew Ferraiuolo, Danfeng Zhang, Andrew C. Myers, G. Edward Suh

SecDCP: secure dynamic cache partitioning for efficient timing channel protection

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Privacy preserving localization for smart automotive systems

Siam U. Hussain, Farinaz Koushanfar

Privacy preserving localization for smart automotive systems

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ageOpt-RMT: compiler-driven variation-aware aging optimization for redundant multithreading

Florian Kriebel, Semeen Rehman, Muhammad Shafique, Jörg Henkel

ageOpt-RMT: compiler-driven variation-aware aging optimization for redundant multithreading

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Spectral graph sparsification in nearly-linear time leveraging efficient spectral perturbation analysis

Zhuo Feng

Spectral graph sparsification in nearly-linear time leveraging efficient spectral perturbation analysis

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Precise error determination of approximated components in sequential circuits with model checking

Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler

Precise error determination of approximated components in sequential circuits with model checking

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Design partitioning for large-scale equivalence checking and functional correction

Grace Wu, Yi-Tin Sun, Jie-Hong R. Jiang

Design partitioning for large-scale equivalence checking and functional correction

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Legalization algorithm for multiple-row height standard cell design

Wing-Kai Chow, Chak-Wa Pui, Evangeline F. Y. Young

Legalization algorithm for multiple-row height standard cell design

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Lower power by voltage stacking: a fine-grained system design approach

Kristof Blutman, Ajay Kapoor, Jacinto Garcia Martinez, Hamed Fatemi, José Pineda de Gyvez

Lower power by voltage stacking: a fine-grained system design approach

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Designing guardbands for instantaneous aging effects

Victor M. van Santen, Hussam Amrouch, Javier Martín-Martínez, Montserrat Nafría, Jörg Henkel

Designing guardbands for instantaneous aging effects

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SwiftGPU: fostering energy efficiency in a near-threshold GPU through a tactical performance boost

Prabal Basu, Hu Chen, Shamik Saha, Koushik Chakraborty, Sanghamitra Roy

SwiftGPU: fostering energy efficiency in a near-threshold GPU through a tactical performance boost

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AVFSM: a framework for identifying and mitigating vulnerabilities in FSMs

Adib Nahiyan, Kan Xiao, Kun Yang, Yier Jin, Domenic Forte, Mark Tehranipoor

AVFSM: a framework for identifying and mitigating vulnerabilities in FSMs

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An area-efficient consolidated configurable error correction for approximate hardware accelerators

Sana Mazahir, Osman Hasan, Rehan Hafiz, Muhammad Shafique, Jörg Henkel

An area-efficient consolidated configurable error correction for approximate hardware accelerators

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Hybrid STT-CMOS designs for reverse-engineering prevention

Theodore Winograd, Hassan Salmani, Hamid Mahmoodi, Kris Gaj, Houman Homayoun

Hybrid STT-CMOS designs for reverse-engineering prevention

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Standard lattices in hardware

James Howe, Ciara Moore, Máire O'Neill, Francesco Regazzoni, Tim Güneysu, K. Beeden

Standard lattices in hardware

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Simplifying deep neural networks for neuromorphic architectures

Jaeyong Chung, Taehwan Shin

Simplifying deep neural networks for neuromorphic architectures

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Efficient transistor-level timing yield estimation via line sampling

Hiromitsu Awano, Takashi Sato

Efficient transistor-level timing yield estimation via line sampling

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Synergistic timing speculation for multi-threaded programs

Atif Yasin, Jeff Jun Zhang, Hu Chen, Siddharth Garg, Sanghamitra Roy, Koushik Chakraborty

Synergistic timing speculation for multi-threaded programs

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Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification

Doowon Lee, Tom Kolan, Arkadiy Morgenshtein, Vitali Sokhin, Ronny Morad, Avi Ziv, Valeria Bertacco

Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification

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Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation

Keith A. Campbell, Leon He, Liwei Yang, Swathi T. Gurumani, Kyle Rupnow, Deming Chen

Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation

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Invited - The case for embedded scalable platforms

Luca P. Carloni

Invited - The case for embedded scalable platforms

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Notifying memories: a case-study on data-flow applications with NoC interfaces implementation

Kevin J. M. Martin, Mostafa Rizk, Martha Johanna Sepúlveda, Jean-Philippe Diguet

Notifying memories: a case-study on data-flow applications with NoC interfaces implementation

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An efficient method for multi-level approximate logic synthesis under error rate constraint

Yi Wu, Weikang Qian

An efficient method for multi-level approximate logic synthesis under error rate constraint

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Invited - Ultra low power integrated transceivers for near-field IoT

Mihai Sanduleanu, Ibrahim Abe M. Elfadel

Invited - Ultra low power integrated transceivers for near-field IoT

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Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM

Huizhang Luo, Jingtong Hu, Liang Shi, Chun Jason Xue, Qingfeng Zhuge

Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM

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Resource budgeting for reliability in reconfigurable architectures

Hongyan Zhang, Lars Bauer, Jörg Henkel

Resource budgeting for reliability in reconfigurable architectures

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Improving high-level synthesis with decoupled data structure optimization

Ritchie Zhao, Gai Liu, Shreesha Srinath, Christopher Batten, Zhiru Zhang

Improving high-level synthesis with decoupled data structure optimization

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A new learning method for inference accuracy, core occupation, and performance co-optimization on TrueNorth chip

Wei Wen, Chunpeng Wu, Yandan Wang, Kent W. Nixon, Qing Wu, Mark Barnell, Hai Li, Yiran Chen

A new learning method for inference accuracy, core occupation, and performance co-optimization on TrueNorth chip

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Predicting electromigration mortality under temperature and product lifetime specifications

Vivek Mishra, Sachin S. Sapatnekar

Predicting electromigration mortality under temperature and product lifetime specifications

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Real-time co-scheduling of multiple dataflow graphs on multi-processor systems

Shin-Haeng Kang, Duseok Kang, Hoeseok Yang, Soonhoi Ha

Real-time co-scheduling of multiple dataflow graphs on multi-processor systems

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Information dispersion for trojan defense through high-level synthesis

S. T. Choden Konigsmark, Deming Chen, Martin D. F. Wong

Information dispersion for trojan defense through high-level synthesis

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MTJ variation monitor-assisted adaptive MRAM write

Shaodi Wang, Hochul Lee, Cecile Grezes, Pedram Khalili, Kang L. Wang, Puneet Gupta

MTJ variation monitor-assisted adaptive MRAM write

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Optimal design of JPEG hardware under the approximate computing paradigm

Farhana Sharmin Snigdha, Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar

Optimal design of JPEG hardware under the approximate computing paradigm

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Similarity-based wakeup management for mobile systems in connected standby

Chun-Hao Kao, Sheng-Wei Cheng, Pi-Cheng Hsiu

Similarity-based wakeup management for mobile systems in connected standby

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Re-target-able software power management framework using SoC data auto-generation

Piyali Goswami, Sushaanth Srirangapathi, Chetan Matad, Stanley Liu

Re-target-able software power management framework using SoC data auto-generation

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EffiTest: efficient delay test and statistical prediction for configuring post-silicon tunable buffers

Grace Li Zhang, Bing Li, Ulf Schlichtmann

EffiTest: efficient delay test and statistical prediction for configuring post-silicon tunable buffers

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Catching the flu: emerging threats from a third party power management unit

Rajesh Jayashankara Shridevi, Chidhambaranathan Rajamanikkam, Koushik Chakraborty, Sanghamitra Roy

Catching the flu: emerging threats from a third party power management unit

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PLL to the rescue: a novel EM fault countermeasure

Noriyuki Miura, Zakaria Najm, Wei He, Shivam Bhasin, Xuan Thuy Ngo, Makoto Nagata, Jean-Luc Danger

PLL to the rescue: a novel EM fault countermeasure

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The cat and mouse in split manufacturing

Yujie Wang, Pu Chen, Jiang Hu, Jeyavijayan Rajendran

The cat and mouse in split manufacturing

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Statistical path tracing in timing graphs

Vasant Rao, Debjit Sinha, Nitin Srimal, Prabhat K. Maurya

Statistical path tracing in timing graphs

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Remote attestation for low-end embedded devices: the prover's perspective

Franz Ferdinand Brasser, Kasper Bonne Rasmussen, Ahmad-Reza Sadeghi, Gene Tsudik

Remote attestation for low-end embedded devices: the prover's perspective

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A framework for verification of SystemC TLM programs with model slicing: a case study

Reza Hajisheykhi, Mohammad Roohitavaf, Ali Ebnenasir, Sandeep S. Kulkarni

A framework for verification of SystemC TLM programs with model slicing: a case study

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NVSim-VXs: an improved NVSim for variation aware STT-RAM simulation

Enes Eken, Linghao Song, Ismail Bayram, Cong Xu, Wujie Wen, Yuan Xie, Yiran Chen

NVSim-VXs: an improved NVSim for variation aware STT-RAM simulation

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Single-tier virtual queuing: an efficacious memory controller architecture for MPSoCs with multiple realtime cores

Yang Song, Kambiz Samadi, Bill Lin

Single-tier virtual queuing: an efficacious memory controller architecture for MPSoCs with multiple realtime cores

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Reliability-aware design to suppress aging

Hussam Amrouch, Behnam Khaleghi, Andreas Gerstlauer, Jörg Henkel

Reliability-aware design to suppress aging

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A novel time and voltage based SAR ADC design with self-learning technique

Abhilash Karnatakam Nagabhushana, Haibo Wang

A novel time and voltage based SAR ADC design with self-learning technique

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Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision

Matthew Poremba, Tao Zhang, Yuan Xie

Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision

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Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture

Po-Han Wang, Cheng-Hsuan Li, Chia-Lin Yang

Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture

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Match-making for monolithic 3D IC: finding the right technology node

Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim

Match-making for monolithic 3D IC: finding the right technology node

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Reducing control bit overhead for X-masking/X-canceling hybrid architecture via pattern partitioning

Jin-Hyun Kang, Nur A. Touba, Joon-Sung Yang

Reducing control bit overhead for X-masking/X-canceling hybrid architecture via pattern partitioning

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Practical statistical static timing analysis with current source models

Debjit Sinha, Vladimir Zolotov, Sheshashayee K. Raghunathan, Michael H. Wood, Kerim Kalafala

Practical statistical static timing analysis with current source models

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A low-power dynamic divider for approximate applications

Soheil Hashemi, R. Iris Bahar, Sherief Reda

A low-power dynamic divider for approximate applications

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Fault injection acceleration by simultaneous injection of non-interacting faults

Mojtaba Ebrahimi, Mohammad Hadi Moshrefpour, Mohammad Saber Golanbari, Mehdi Baradaran Tahoori

Fault injection acceleration by simultaneous injection of non-interacting faults

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Relevance vector and feature machine for statistical analog circuit characterization and built-in self-test optimization

Honghuang Lin, Peng Li

Relevance vector and feature machine for statistical analog circuit characterization and built-in self-test optimization

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Serial T0: approximate bus encoding for energy-efficient transmission of sensor signals

Daniele Jahier Pagliari, Enrico Macii, Massimo Poncino

Serial T0: approximate bus encoding for energy-efficient transmission of sensor signals

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Invited - Airtouch: a novel single layer 3D touch sensing system for human/mobile devices interactions

Li Du, Chun-Chen Liu, Adrian Tang, Yan Zhang, Yilei Li, Kye Cheung, Mau-Chung Frank Chang

Invited - Airtouch: a novel single layer 3D touch sensing system for human/mobile devices interactions

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Invited - Specification and modeling for systems-on-chip security verification

Sharad Malik, Pramod Subramanyan

Invited - Specification and modeling for systems-on-chip security verification

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Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs

Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Luis Gabriel Murillo

Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs

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QB-trees: towards an optimal topological representation and its applications to analog layout designs

I-Peng Wu, Hung-Chih Ou, Yao-Wen Chang

QB-trees: towards an optimal topological representation and its applications to analog layout designs

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Invited - Who is the major threat to tomorrow's security?: you, the hardware designer

Wayne Burleson, Onur Mutlu, Mohit Tiwari

Invited - Who is the major threat to tomorrow's security?: you, the hardware designer

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Comprehensive optimization of scan chain timing during late-stage IC implementation

Kun Young Chung, Andrew B. Kahng, Jiajia Li

Comprehensive optimization of scan chain timing during late-stage IC implementation

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nZDC: a compiler technique for near zero silent data corruption

Moslem Didehban, Aviral Shrivastava

nZDC: a compiler technique for near zero silent data corruption

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Invited - Optimizing device reliability effects at the intersection of physics, circuits, and architecture

Deepashree Sengupta, Vivek Mishra, Sachin S. Sapatnekar

Invited - Optimizing device reliability effects at the intersection of physics, circuits, and architecture

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AOS: adaptive overwrite scheme for energy-efficient MLC STT-RAM cache

Xunchao Chen, Navid Khoshavi, Jian Zhou, Dan Huang, Ronald F. DeMara, Jun Wang, Wujie Wen, Yiran Chen

AOS: adaptive overwrite scheme for energy-efficient MLC STT-RAM cache

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Timing-driven cell placement optimization for early slack histogram compression

Chau-Chin Huang, Yen-Chun Liu, Yu-Sheng Lu, Yun-Chih Kuo, Yao-Wen Chang, Sy-Yen Kuo

Timing-driven cell placement optimization for early slack histogram compression

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BLESS: a simple and efficient scheme for prolonging PCM lifetime

Marjan Asadinia, Majid Jalili, Hamid Sarbazi-Azad

BLESS: a simple and efficient scheme for prolonging PCM lifetime

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A fast simulator for the analysis of sub-threshold thermal noise transients

Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky

A fast simulator for the analysis of sub-threshold thermal noise transients

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Procedural capacitor placement in differential charge-scaling converters by nonlinearity analysis

Florin Burcea, Husni M. Habal, Helmut E. Graeb

Procedural capacitor placement in differential charge-scaling converters by nonlinearity analysis

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Extended statistical element selection: a calibration method for high resolution in analog/RF designs

Renzhi Liu, Jeffrey A. Weldon, Larry T. Pileggi

Extended statistical element selection: a calibration method for high resolution in analog/RF designs

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Minimum-implant-area-aware detailed placement with spacing constraints

Kai-Han Tseng, Yao-Wen Chang, Charles C. C. Liu

Minimum-implant-area-aware detailed placement with spacing constraints

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A distributed timing analysis framework for large designs

Tsung-Wei Huang, Martin D. F. Wong, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran

A distributed timing analysis framework for large designs

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Flip-flop clustering by weighted K-means algorithm

Gang Wu, Yue Xu, Dean Wu, Manoj Ragupathy, Yu-Yen Mo, Chris C. N. Chu

Flip-flop clustering by weighted K-means algorithm

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Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits

Qicheng Huang, Chenlei Fang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li

Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits

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Exploration of associative power management with instruction governed operation for ultra-low power design

Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu

Exploration of associative power management with instruction governed operation for ultra-low power design

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Minimizing the energy-delay product of SRAM arrays using a device-circuit-architecture co-optimization framework

Alireza Shafaei, Hassan Afzali-Kusha, Massoud Pedram

Minimizing the energy-delay product of SRAM arrays using a device-circuit-architecture co-optimization framework

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Columba: co-layout synthesis for continuous-flow microfluidic biochips

Tsun-Ming Tseng, Mengchu Li, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann

Columba: co-layout synthesis for continuous-flow microfluidic biochips

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DAG-aware logic synthesis of datapaths

Cunxi Yu, Maciej J. Ciesielski, Mihir Choudhury, Andrew Sullivan

DAG-aware logic synthesis of datapaths

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Switched by input: power efficient structure for RRAM-based convolutional neural network

Lixue Xia, Tianqi Tang, Wenqin Huangfu, Ming Cheng, Xiling Yin, Boxun Li, Yu Wang, Huazhong Yang

Switched by input: power efficient structure for RRAM-based convolutional neural network

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Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing

Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann

Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing

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Clear: c̲ross-l̲ayer e̲xploration for a̲rchitecting r̲esilience combining hardware and software techniques to tolerate soft errors in processor cores

Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra

Clear: c̲ross-l̲ayer e̲xploration for a̲rchitecting r̲esilience combining hardware and software techniques to tolerate soft errors in processor cores

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Statistical fault injection for impact-evaluation of timing errors on application performance

Jeremy Constantin, Andreas Peter Burg, Zheng Wang, Anupam Chattopadhyay, Georgios Karakonstantis

Statistical fault injection for impact-evaluation of timing errors on application performance

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Low-power approximate convolution computing unit with domain-wall motion based "spin-memristor" for image processing applications

Yong Shim, Abhronil Sengupta, Kaushik Roy

Low-power approximate convolution computing unit with domain-wall motion based "spin-memristor" for image processing applications

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Accelerating soft-error-rate (SER) estimation in the presence of single event transients

Ji Li, Jeffrey Draper

Accelerating soft-error-rate (SER) estimation in the presence of single event transients

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Utilization bounds on allocating rate-monotonic scheduled multi-mode tasks on multiprocessor systems

Wen-Hung Huang, Jian-Jia Chen

Utilization bounds on allocating rate-monotonic scheduled multi-mode tasks on multiprocessor systems

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Physics-based full-chip TDDB assessment for BEOL interconnects

Xin Huang, Valeriy Sukharev, Zhongdong Qi, Taeyoung Kim, Sheldon X.-D. Tan

Physics-based full-chip TDDB assessment for BEOL interconnects

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An MIG-based compiler for programmable logic-in-memory architectures

Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli

An MIG-based compiler for programmable logic-in-memory architectures

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Redundant via insertion for multiple-patterning directed-self-assembly lithography

Seongbo Shim, Woohyun Chung, Youngsoo Shin

Redundant via insertion for multiple-patterning directed-self-assembly lithography

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A low-power carry cut-back approximate adder with fixed-point implementation and floating-point precision

Vincent Camus, Jeremy Schlachter, Christian C. Enz

A low-power carry cut-back approximate adder with fixed-point implementation and floating-point precision

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Shift sprinting: fine-grained temperature-aware NoC-based MCSoC architecture in dark silicon age

Amin Rezaei, Danella Zhao, Masoud Daneshtalab, Hongyi Wu

Shift sprinting: fine-grained temperature-aware NoC-based MCSoC architecture in dark silicon age

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Optimal and fast throughput evaluation of CSDF

Bruno Bodin, Alix Munier Kordon, Benoît Dupont de Dinechin

Optimal and fast throughput evaluation of CSDF

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Exploiting design-for-debug for flexible SoC security architecture

Abhishek Basak, Swarup Bhunia, Sandip Ray

Exploiting design-for-debug for flexible SoC security architecture

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Achieving lightweight multicast in asynchronous networks-on-chip using local speculation

Kshitij Bhardwaj, Steven M. Nowick

Achieving lightweight multicast in asynchronous networks-on-chip using local speculation

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TEMP: thread batch enabled memory partitioning for GPU

Mengjie Mao, Wujie Wen, Xiaoxiao Liu, Jingtong Hu, Danghui Wang, Yiran Chen, Hai Li

TEMP: thread batch enabled memory partitioning for GPU

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MORPh: mobile OLED-friendly recording and playback system for low power video streaming

Xiang Chen, Jiachen Mao, Jiafei Gao, Kent W. Nixon, Yiran Chen

MORPh: mobile OLED-friendly recording and playback system for low power video streaming

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Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability

Nathaniel Ross Pinckney, Lucian Shifren, Brian Cline, Saurabh Sinha, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David Blaauw

Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability

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Distributed scheduling for many-cores using cooperative game theory

Anuj Pathania, Vanchinathan Venkataramani, Muhammad Shafique, Tulika Mitra, Jörg Henkel

Distributed scheduling for many-cores using cooperative game theory

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Lin-analyzer: a high-level performance analysis tool for FPGA-based accelerators

Guanwen Zhong, Alok Prakash, Yun Liang, Tulika Mitra, Smaïl Niar

Lin-analyzer: a high-level performance analysis tool for FPGA-based accelerators

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Invited - Can IoT be secured: emerging challenges in connecting the unconnected

Nancy Cam-Winget, Ahmad-Reza Sadeghi, Yier Jin

Invited - Can IoT be secured: emerging challenges in connecting the unconnected

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Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays

Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei

Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays

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Invited - Cross-layer approximations for neuromorphic computing: from devices to circuits and systems

Priyadarshini Panda, Abhronil Sengupta, Syed Shakib Sarwar, Gopalakrishnan Srinivasan, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy

Invited - Cross-layer approximations for neuromorphic computing: from devices to circuits and systems

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SECRET: smartly EnCRypted energy efficient non-volatile memories

Shivam Swami, Joydeep Rakshit, Kartik Mohanram

SECRET: smartly EnCRypted energy efficient non-volatile memories

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A novel cross-layer framework for early-stage power delivery and architecture co-exploration

Cheng Zhuo, Kassan Unda, Yiyu Shi, Wei-Kai Shih

A novel cross-layer framework for early-stage power delivery and architecture co-exploration

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High-level synthesis for micro-electrode-dot-array digital microfluidic biochips

Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Tsung-Yi Ho, Krishnendu Chakrabarty, Chen-Yi Lee

High-level synthesis for micro-electrode-dot-array digital microfluidic biochips

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DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors

Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li

DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors

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HW/SW co-design of nonvolatile IO system in energy harvesting sensor nodes for optimal data acquisition

Zewei Li, Yongpan Liu, Daming Zhang, Chun Jason Xue, Zhangyuan Wang, Xin Shi, Wenyu Sun, Jiwu Shu, Huazhong Yang

HW/SW co-design of nonvolatile IO system in energy harvesting sensor nodes for optimal data acquisition

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PDS: pseudo-differential sensing scheme for STT-MRAM

Wang Kang, Tingting Pang, Bi Wu, Weifeng Lv, Youguang Zhang, Guangyu Sun, Weisheng Zhao

PDS: pseudo-differential sensing scheme for STT-MRAM

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Practical public PUF enabled by solving max-flow problem on chip

Meng Li, Jin Miao, Kai Zhong, David Z. Pan

Practical public PUF enabled by solving max-flow problem on chip

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PICO: mitigating heterodyne crosstalk due to process variations and intermodulation effects in photonic NoCs

Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha

PICO: mitigating heterodyne crosstalk due to process variations and intermodulation effects in photonic NoCs

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Incremental layer assignment for critical path timing

Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan

Incremental layer assignment for critical path timing

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A semantics-aware design for mounting remote sensors on mobile systems

Yu-Wen Jong, Pi-Cheng Hsiu, Sheng-Wei Cheng, Tei-Wei Kuo

A semantics-aware design for mounting remote sensors on mobile systems

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Improving performance and lifetime of NAND storage systems using relaxed program sequence

Jisung Park, Jaeyong Jeong, Sungjin Lee, Youngsun Song, Jihong Kim

Improving performance and lifetime of NAND storage systems using relaxed program sequence

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Efficient design space exploration via statistical sampling and AdaBoost learning

Dandan Li, Shuzhen Yao, Yu-Hang Liu, Senzhang Wang, Xian-He Sun

Efficient design space exploration via statistical sampling and AdaBoost learning

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Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis

Mathias Soeken, Anupam Chattopadhyay

Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis

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Invited - Integrated millimeter-wave/terahertz sensor systems for near-field IoT

Payam Heydari

Invited - Integrated millimeter-wave/terahertz sensor systems for near-field IoT

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Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration

Yixiao Ding, Chris C. N. Chu, Wai-Kei Mak

Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration

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Efficient performance modeling of analog integrated circuits via kernel density based sparse regression

Chenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li

Efficient performance modeling of analog integrated circuits via kernel density based sparse regression

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A quantum annealing approach for boolean satisfiability problem

Juexiao Su, Tianheng Tu, Lei He

A quantum annealing approach for boolean satisfiability problem

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Invited - Cross-layer approaches for soft error modeling and mitigation

Mojtaba Ebrahimi, Mehdi Baradaran Tahoori

Invited - Cross-layer approaches for soft error modeling and mitigation

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GarbledCPU: a MIPS processor for secure computation in hardware

Ebrahim M. Songhori, Shaza Zeitouni, Ghada Dessouky, Thomas Schneider, Ahmad-Reza Sadeghi, Farinaz Koushanfar

GarbledCPU: a MIPS processor for secure computation in hardware

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Distributed on-chip regulation: theoretical stability foundation, over-design reduction and performance optimization

Xin Zhan, Peng Li, Edgar Sánchez-Sinencio

Distributed on-chip regulation: theoretical stability foundation, over-design reduction and performance optimization

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Formal reliability analysis of switched ethernet automotive networks under transient transmission errors

Fedor Smirnov, Michael Glaß, Felix Reimann, Jürgen Teich

Formal reliability analysis of switched ethernet automotive networks under transient transmission errors

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Accurate phase-level cross-platform power and performance estimation

Xinnian Zheng, Lizy K. John, Andreas Gerstlauer

Accurate phase-level cross-platform power and performance estimation

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A model-driven approach to warp/thread-block level GPU cache bypassing

Hongwen Dai, Chao Li, Huiyang Zhou, Saurabh Gupta, Christos Kartsaklis, Mike Mantor

A model-driven approach to warp/thread-block level GPU cache bypassing

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Invited - Cross-layer approximate computing: from logic to architectures

Muhammad Shafique, Rehan Hafiz, Semeen Rehman, Walaa El-Harouni, Jörg Henkel

Invited - Cross-layer approximate computing: from logic to architectures

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Area optimization of resilient designs guided by a mixed integer geometric program

Hsin-Ho Huang, Huimei Cheng, Chris C. N. Chu, Peter A. Beerel

Area optimization of resilient designs guided by a mixed integer geometric program

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C-brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization

Lili Song, Ying Wang, Yinhe Han, Xin Zhao, Bosheng Liu, Xiaowei Li

C-brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization

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A probabilistic scheduling framework for mixed-criticality systems

Alejandro Masrur

A probabilistic scheduling framework for mixed-criticality systems

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A quantitative analysis on microarchitectures of modern CPU-FPGA platforms

Young-kyu Choi, Jason Cong, Zhenman Fang, Yuchen Hao, Glenn Reinman, Peng Wei

A quantitative analysis on microarchitectures of modern CPU-FPGA platforms

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Random modulo: a new processor cache design for real-time critical systems

Carles Hernández, Jaume Abella, Andrea Gianarro, Jan Andersson, Francisco J. Cazorla

Random modulo: a new processor cache design for real-time critical systems

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Author Comments: This invention is integrated on a RTL implementation of an enhanced Cobham Gaisler LEON3 processor. The full bitstream, where this invention is integrated in all first level data and instruction caches can be requested to Cobham Gaisler as announced in their website: http://www.gaisler.com/index.php/products/processors/leon3
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Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package

Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang

Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package

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Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories

Shuangchen Li, Cong Xu, Qiaosha Zou, Jishen Zhao, Yu Lu, Yuan Xie

Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories

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Energy efficient computation with asynchronous races

Advait Madhavan, Timothy Sherwood, Dmitri B. Strukov

Energy efficient computation with asynchronous races

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Correlated Bayesian Model Fusion: efficient performance modeling of large-scale tunable analog/RF integrated circuits

Fa Wang, Xin Li

Correlated Bayesian Model Fusion: efficient performance modeling of large-scale tunable analog/RF integrated circuits

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Strategy without tactics: policy-agnostic hardware-enhanced control-flow integrity

Dean Sullivan, Orlando Arias, Lucas Davi, Per Larsen, Ahmad-Reza Sadeghi, Yier Jin

Strategy without tactics: policy-agnostic hardware-enhanced control-flow integrity

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Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead

Hehe Li, Yongpan Liu, Chenchen Fu, Chun Jason Xue, Donglai Xiang, Jinshan Yue, Jinyang Li, Daming Zhang, Jingtong Hu, Huazhong Yang

Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead

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MIRROR: symmetric timing analysis for real-time tasks on multicore platforms with shared resources

Wen-Hung Huang, Jian-Jia Chen, Jan Reineke

MIRROR: symmetric timing analysis for real-time tasks on multicore platforms with shared resources

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DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family

Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li

DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family

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StitchUp: automatic control flow protection for high level synthesis circuits

Shane T. Fleming, David B. Thomas

StitchUp: automatic control flow protection for high level synthesis circuits

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An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems

Paolo Mantovani, Emilio G. Cota, Kevin Tien, Christian Pilato, Giuseppe Di Guglielmo, Kenneth L. Shepard, Luca P. Carloni

An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems

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Plug-n-learn: automatic learning of computational algorithms in human-centered internet-of-things applications

Seyed Ali Rokni, Hassan Ghasemzadeh

Plug-n-learn: automatic learning of computational algorithms in human-centered internet-of-things applications

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A real-time energy-efficient superpixel hardware accelerator for mobile computer vision applications

Injoon Hong, Jason Clemons, Rangharajan Venkatesan, Iuri Frosio, Brucek Khailany, Stephen W. Keckler

A real-time energy-efficient superpixel hardware accelerator for mobile computer vision applications

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Invited - Cross-layer modeling and optimization for electromigration induced reliability

Taeyoung Kim, Zeyu Sun, Chase Cook, Hengyang Zhao, Ruiwen Li, Daniel Wong, Sheldon X.-D. Tan

Invited - Cross-layer modeling and optimization for electromigration induced reliability

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Multiple patterning layout decomposition considering complex coloring rules

Hua-Yu Chang, Iris Hui-Ru Jiang

Multiple patterning layout decomposition considering complex coloring rules

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Approximate bitcoin mining

Matthew Vilim, Henry Duwe, Rakesh Kumar

Approximate bitcoin mining

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Invited - Towards fail-operational ethernet based in-vehicle networks

Mischa Möstl, Daniel Thiele, Rolf Ernst

Invited - Towards fail-operational ethernet based in-vehicle networks

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Invited - Approximate computing with partially unreliable dynamic random access memory - approximate DRAM

Matthias Jung, Deepak M. Mathew, Christian Weis, Norbert Wehn

Invited - Approximate computing with partially unreliable dynamic random access memory - approximate DRAM

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On harmonic fixed-priority scheduling of periodic real-time tasks with constrained deadlines

Tianyi Wang, Qiushi Han, Shi Sha, Wujie Wen, Gang Quan, Meikang Qiu

On harmonic fixed-priority scheduling of periodic real-time tasks with constrained deadlines

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Invited - A 2.2 GHz SRAM with high temperature variation immunity for deep learning application under 28nm

Chun-Chen Liu, Yen-Hsiang Wang, Yilei Li, Chien-Heng Wong, Tien Pei Chou, Young-Kai Chen, M.-C. Frank Chang

Invited - A 2.2 GHz SRAM with high temperature variation immunity for deep learning application under 28nm

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An MPSoC for energy-efficient database query processing

Sebastian Haas, Oliver Arnold, Benedikt Nöthen, Stefan Scholze, Georg Ellguth, Andreas Dixius, Sebastian Höppner, Stefan Schiefer, Stephan Hartmann, Stephan Henker, Thomas Hocker, Jörg Schreiter, Holger Eisenreich, Jens-Uwe Schlüßler, Dennis Walter, Tobias Seifert, Friedrich Pauls, Mattis Hasler, Yong Chen, Hermann Hensel, Sadia Moriam, Emil Matús, Christian Mayr, René Schüffny, Gerhard P. Fettweis

An MPSoC for energy-efficient database query processing

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Physical unclonable functions-based linear encryption against code reuse attacks

Pengfei Qiu, Yongqiang Lyu, Jiliang Zhang, Xingwei Wang, Di Zhai, Dongsheng Wang, Gang Qu

Physical unclonable functions-based linear encryption against code reuse attacks

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Invited - Things, trouble, trust: on building trust in IoT systems

Tigist Abera, N. Asokan, Lucas Davi, Farinaz Koushanfar, Andrew Paverd, Ahmad-Reza Sadeghi, Gene Tsudik

Invited - Things, trouble, trust: on building trust in IoT systems

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Invited - A box of dots: using scan-based path delay test for timing verification

Alfred L. Crouch, John C. Potter

Invited - A box of dots: using scan-based path delay test for timing verification

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VR-scale: runtime dynamic phase scaling of processor voltage regulators for improving power efficiency

Hadi Asghari Moghaddam, Hamid Reza Ghasemi, Abhishek Arvind Sinkar, Indrani Paul, Nam Sung Kim

VR-scale: runtime dynamic phase scaling of processor voltage regulators for improving power efficiency

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Write-back aware shared last-level cache management for hybrid main memory

Deshan Zhang, Lei Ju, Mengying Zhao, Xiang Gao, Zhiping Jia

Write-back aware shared last-level cache management for hybrid main memory

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Invited - Context-aware energy-efficient communication for IoT sensor nodes

Shreyas Sen

Invited - Context-aware energy-efficient communication for IoT sensor nodes

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Integration of multi-sensor occupancy grids into automotive ECUs

Tiana A. Rakotovao, Julien Mottin, Diego Puschini, Christian Laugier

Integration of multi-sensor occupancy grids into automotive ECUs

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Improving mobile gaming performance through cooperative CPU-GPU thermal management

Alok Prakash, Hussam Amrouch, Muhammad Shafique, Tulika Mitra, Jörg Henkel

Improving mobile gaming performance through cooperative CPU-GPU thermal management

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Architecting energy-efficient STT-RAM based register file on GPGPUs via delta compression

Hang Zhang, Xuhao Chen, Nong Xiao, Fang Liu

Architecting energy-efficient STT-RAM based register file on GPGPUs via delta compression

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