| Title: |
Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture |
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| Authors: |
Po-Han Wang |
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National Taiwan University Taipei, Taiwan R.O.C., Dept. of Computer Science and Information Engineering
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| Cheng-Hsuan Li |
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National Taiwan University Taipei, Taiwan R.O.C., Dept. of Computer Science and Information Engineering
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| Chia-Lin Yang |
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National Taiwan University Taipei, Taiwan R.O.C., Dept. of Computer Science and Information Engineering
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National Taiwan University Taipei, Taiwan R.O.C., Graduate Institute of Networking and Multimedia
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Academia Sinica Taipei, Taiwan R.O.C., Research Center for Information Technology Innovation
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| Sharing: |
Unknown
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| Verification: |
Authors have
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information
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none
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| DBLP Key: |
conf/dac/WangLY16
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