IEEE/ACM International Symposium on Microarchitecture, MICRO 2016


Title/Authors Title Research Artifacts
[?] A research artifact is any by-product of a research project that is not directly included in the published research paper. In Computer Science research this is often source code and data sets, but it could also be media, documentation, inputs to proof assistants, shell-scripts to run experiments, etc.
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Reducing data movement energy via online data clustering and encoding

Shibo Wang, Engin Ipek

Reducing data movement energy via online data clustering and encoding

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pTask: A smart prefetching scheme for OS intensive applications

Prathmesh Kallurkar, Smruti R. Sarangi

pTask: A smart prefetching scheme for OS intensive applications

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Quantifying and improving the efficiency of hardware-based mobile malware detectors

Mikhail Kazdagli, Vijay Janapa Reddi, Mohit Tiwari

Quantifying and improving the efficiency of hardware-based mobile malware detectors

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Path confidence based lookahead prefetching

Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy, Chris Wilkerson, Zeshan Chishti

Path confidence based lookahead prefetching

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HARE: Hardware accelerator for regular expressions

Vaibhav Gogte, Aasheesh Kolli, Michael J. Cafarella, Loris D'Antoni, Thomas F. Wenisch

HARE: Hardware accelerator for regular expressions

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Continuous shape shifting: Enabling loop co-optimization via near-free dynamic code rewriting

Animesh Jain, Michael A. Laurenzano, Lingjia Tang, Jason Mars

Continuous shape shifting: Enabling loop co-optimization via near-free dynamic code rewriting

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NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints

Yu Ji, Youhui Zhang, Shuangchen Li, Ping Chi, Cihang Jiang, Peng Qu, Yuan Xie, Wenguang Chen

NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints

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Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems

Hadi Asghari Moghaddam, Young Hoon Son, Jung Ho Ahn, Nam Sung Kim

Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems

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CANDY: Enabling coherent DRAM caches for multi-node systems

Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi

CANDY: Enabling coherent DRAM caches for multi-node systems

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vDNN: Virtualized deep neural networks for scalable, memory-efficient neural network design

Minsoo Rhu, Natalia Gimelshein, Jason Clemons, Arslan Zulfiqar, Stephen W. Keckler

vDNN: Virtualized deep neural networks for scalable, memory-efficient neural network design

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Cambricon-X: An accelerator for sparse neural networks

Shijin Zhang, Zidong Du, Lei Zhang, Huiying Lan, Shaoli Liu, Ling Li, Qi Guo, Tianshi Chen, Yunji Chen

Cambricon-X: An accelerator for sparse neural networks

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Dynamic error mitigation in NoCs using intelligent prediction techniques

Dominic DiTomaso, Travis Boraten, Avinash Kodi, Ahmed Louri

Dynamic error mitigation in NoCs using intelligent prediction techniques

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Ti-states: Processor power management in the temperature inversion region

Yazhou Zu, Wei Huang, Indrani Paul, Vijay Janapa Reddi

Ti-states: Processor power management in the temperature inversion region

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Approxilyzer: Towards a systematic framework for instruction-level approximate computing and its application to hardware resiliency

Radha Venkatagiri, Abdulrahman Mahmoud, Siva Kumar Sastry Hari, Sarita V. Adve

Approxilyzer: Towards a systematic framework for instruction-level approximate computing and its application to hardware resiliency

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Author Comments: The Approxilyzer tool has been released and is located at https://cs.illinois.edu/approxilyzer.
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A cloud-scale acceleration architecture

Adrian M. Caulfield, Eric S. Chung, Andrew Putnam, Hari Angepat, Jeremy Fowers, Michael Haselman, Stephen Heil, Matt Humphrey, Puneet Kaur, Joo-Young Kim, Daniel Lo, Todd Massengill, Kalin Ovtcharov, Michael Papamichael, Lisa Woods, Sitaram Lanka, Derek Chiou, Doug Burger

A cloud-scale acceleration architecture

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Register sharing for equality prediction

Arthur Perais, Fernando A. Endo, André Seznec

Register sharing for equality prediction

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Fused-layer CNN accelerators

Manoj Alwani, Han Chen, Michael Ferdman, Peter Milder

Fused-layer CNN accelerators

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CrystalBall: Statically analyzing runtime behavior via deep sequence learning

Stephen Zekany, Daniel Rings, Nathan Harada, Michael A. Laurenzano, Lingjia Tang, Jason Mars

CrystalBall: Statically analyzing runtime behavior via deep sequence learning

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NeSC: Self-virtualizing nested storage controller

Yonatan Gottesman, Yoav Etsion

NeSC: Self-virtualizing nested storage controller

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A patch memory system for image processing and computer vision

Jason Clemons, Chih-Chi Cheng, Iuri Frosio, Daniel R. Johnson, Stephen W. Keckler

A patch memory system for image processing and computer vision

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Towards efficient server architecture for virtualized network function deployment: Implications and implementations

Yang Hu, Tao Li

Towards efficient server architecture for virtualized network function deployment: Implications and implementations

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Contention-based congestion management in large-scale networks

Gwangsun Kim, Changhyun Kim, Jiyun Jeong, Mike Parker, John Kim

Contention-based congestion management in large-scale networks

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OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures

Jia Zhan, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Yuan Xie

OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures

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Improving energy efficiency of DRAM by exploiting half page row access

Heonjae Ha, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz

Improving energy efficiency of DRAM by exploiting half page row access

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GRAPE: Minimizing energy for GPU applications with performance requirements

Muhammad Husni Santriaji, Henry Hoffmann

GRAPE: Minimizing energy for GPU applications with performance requirements

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Jump over ASLR: Attacking branch predictors to bypass ASLR

Dmitry Evtyushkin, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh

Jump over ASLR: Attacking branch predictors to bypass ASLR

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Efficient data supply for hardware accelerators with prefetching and access/execute decoupling

Tao Chen, G. Edward Suh

Efficient data supply for hardware accelerators with prefetching and access/execute decoupling

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Efficient kernel synthesis for performance portable programming

Li-Wen Chang, Izzat El Hajj, Christopher I. Rodrigues, Juan Gómez-Luna, Wen-mei W. Hwu

Efficient kernel synthesis for performance portable programming

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Data-centric execution of speculative parallel programs

Mark C. Jeffrey, Suvinay Subramanian, Maleen Abeydeera, Joel S. Emer, Daniel Sanchez

Data-centric execution of speculative parallel programs

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Zorua: A holistic approach to resource virtualization in GPUs

Nandita Vijaykumar, Kevin Hsieh, Gennady Pekhimenko, Samira Manabi Khan, Ashish Shrestha, Saugata Ghose, Adwait Jog, Phillip B. Gibbons, Onur Mutlu

Zorua: A holistic approach to resource virtualization in GPUs

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Co-designing accelerators and SoC interfaces using gem5-Aladdin

Yakun Sophia Shao, Sam Likun Xi, Vijayalakshmi Srinivasan, Gu-Yeon Wei, David M. Brooks

Co-designing accelerators and SoC interfaces using gem5-Aladdin

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An ultra low-power hardware accelerator for automatic speech recognition

Reza Yazdani, Albert Segura, Jose-Maria Arnau, Antonio Gonzalez

An ultra low-power hardware accelerator for automatic speech recognition

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Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks

Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert C. N. Pilawa-Podgurski, Ulya R. Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas

Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks

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Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs

Naifeng Jing, Jianfei Wang, Fengfeng Fan, Wenkang Yu, Li Jiang, Chao Li, Xiaoyao Liang

Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs

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KLAP: Kernel launch aggregation and promotion for optimizing dynamic parallelism

Izzat El Hajj, Juan Gómez-Luna, Cheng Li, Li-Wen Chang, Dejan S. Milojicic, Wen-mei W. Hwu

KLAP: Kernel launch aggregation and promotion for optimizing dynamic parallelism

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Spectral profiling: Observer-effect-free profiling by monitoring EM emanations

Nader Sehatbakhsh, Alireza Nazari, Alenka G. Zajic, Milos Prvulovic

Spectral profiling: Observer-effect-free profiling by monitoring EM emanations

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Perceptron learning for reuse prediction

Elvira Teran, Zhe Wang, Daniel A. Jiménez

Perceptron learning for reuse prediction

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SABRes: Atomic object reads for in-memory rack-scale computing

Alexandros Daglis, Dmitrii Ustiugov, Stanko Novakovic, Edouard Bugnion, Babak Falsafi, Boris Grot

SABRes: Atomic object reads for in-memory rack-scale computing

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Bridging the I/O performance gap for big data workloads: A new NVDIMM-based approach

Renhai Chen, Zili Shao, Tao Li

Bridging the I/O performance gap for big data workloads: A new NVDIMM-based approach

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Dictionary sharing: An efficient cache compression scheme for compressed caches

Biswabandan Panda, André Seznec

Dictionary sharing: An efficient cache compression scheme for compressed caches

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Keynotes: Internet of Things: History and hype, technology and policy

Margaret Martonosi

Keynotes: Internet of Things: History and hype, technology and policy

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Delegated persist ordering

Aasheesh Kolli, Jeff Rosen, Stephan Diestelhorst, Ali G. Saidi, Steven Pelley, Sihang Liu, Peter M. Chen, Thomas F. Wenisch

Delegated persist ordering

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The microarchitecture of a real-time robot motion planning accelerator

Sean Murray, William Floyd-Jones, Ying Qi, George Konidaris, Daniel J. Sorin

The microarchitecture of a real-time robot motion planning accelerator

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MIMD synchronization on SIMT architectures

Ahmed ElTantawy, Tor M. Aamodt

MIMD synchronization on SIMT architectures

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Chainsaw: Von-neumann accelerators to leverage fused instruction chains

Amirali Sharifian, Snehasish Kumar, Apala Guha, Arrvindh Shriraman

Chainsaw: Von-neumann accelerators to leverage fused instruction chains

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Exploiting semantic commutativity in hardware speculation

Guowei Zhang, Virginia Chiu, Daniel Sanchez

Exploiting semantic commutativity in hardware speculation

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The Bunker Cache for spatio-value approximation

Joshua San Miguel, Jorge Albericio, Natalie D. Enright Jerger, Aamer Jaleel

The Bunker Cache for spatio-value approximation

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Lazy release consistency for GPUs

Johnathan Alsop, Marc S. Orr, Bradford M. Beckmann, David A. Wood

Lazy release consistency for GPUs

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Redefining QoS and customizing the power management policy to satisfy individual mobile users

Kaige Yan, Xingyao Zhang, Jingweijia Tan, Xin Fu

Redefining QoS and customizing the power management policy to satisfy individual mobile users

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Concise loads and stores: The case for an asymmetric compute-memory architecture for approximation

Animesh Jain, Parker Hill, Shih-Chieh Lin, Muneeb Khan, Md E. Haque, Michael A. Laurenzano, Scott A. Mahlke, Lingjia Tang, Jason Mars

Concise loads and stores: The case for an asymmetric compute-memory architecture for approximation

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From high-level deep neural models to FPGAs

Hardik Sharma, Jongse Park, Divya Mahajan, Emmanuel Amaro, Joon Kyung Kim, Chenkai Shao, Asit Mishra, Hadi Esmaeilzadeh

From high-level deep neural models to FPGAs

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Stripes: Bit-serial deep neural network computing

Patrick Judd, Jorge Albericio, Tayler H. Hetherington, Tor M. Aamodt, Andreas Moshovos

Stripes: Bit-serial deep neural network computing

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Graphicionado: A high-performance and energy-efficient accelerator for graph analytics

Tae Jun Ham, Lisa Wu, Narayanan Sundaram, Nadathur Satish, Margaret Martonosi

Graphicionado: A high-performance and energy-efficient accelerator for graph analytics

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Improving bank-level parallelism for irregular applications

Xulong Tang, Mahmut T. Kandemir, Praveen Yedlapalli, Jagadish Kotra

Improving bank-level parallelism for irregular applications

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Racer: TSO consistency via race detection

Alberto Ros, Stefanos Kaxiras

Racer: TSO consistency via race detection

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Evaluating programmable architectures for imaging and vision applications

Artem Vasilyev, Nikhil Bhagdikar, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz

Evaluating programmable architectures for imaging and vision applications

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ReplayConfusion: Detecting cache-based covert channel attacks using record and replay

Mengjia Yan, Yasser Shalabi, Josep Torrellas

ReplayConfusion: Detecting cache-based covert channel attacks using record and replay

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C3D: Mitigating the NUMA bottleneck via coherent DRAM caches

Cheng-Chieh Huang, Rakesh Kumar, Marco Elver, Boris Grot, Vijay Nagarajan

C3D: Mitigating the NUMA bottleneck via coherent DRAM caches

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PoisonIvy: Safe speculation for secure memory

Tamara Silbergleit Lehman, Andrew D. Hilton, Benjamin C. Lee

PoisonIvy: Safe speculation for secure memory

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Continuous runahead: Transparent hardware acceleration for memory intensive workloads

Milad Hashemi, Onur Mutlu, Yale N. Patt

Continuous runahead: Transparent hardware acceleration for memory intensive workloads

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Low-cost soft error resilience with unified data verification and fine-grained recovery for acoustic sensor based detection

Qingrui Liu, Changhee Jung, Dongyoon Lee, Devesh Tiwari

Low-cost soft error resilience with unified data verification and fine-grained recovery for acoustic sensor based detection

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A unified memory network architecture for in-memory computing in commodity servers

Jia Zhan, Itir Akgun, Jishen Zhao, Al Davis, Paolo Faraboschi, Yuangang Wang, Yuan Xie

A unified memory network architecture for in-memory computing in commodity servers

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