| Title/Authors | Title | Research Artifacts
[?] A research
artifact is any by-product of a research project that is not
directly included in the published research paper. In Computer
Science research this is often source code and data sets, but
it could also be media, documentation, inputs to proof
assistants, shell-scripts to run experiments, etc.
|
Details |
|---|
|
Reducing data movement energy via online data clustering and encoding Shibo Wang, Engin Ipek |
Reducing data movement energy via online data clustering and encoding Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
pTask: A smart prefetching scheme for OS intensive applications Prathmesh Kallurkar, Smruti R. Sarangi |
pTask: A smart prefetching scheme for OS intensive applications Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Quantifying and improving the efficiency of hardware-based mobile malware detectors Mikhail Kazdagli, Vijay Janapa Reddi, Mohit Tiwari |
Quantifying and improving the efficiency of hardware-based mobile malware detectors Details |
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
|
Path confidence based lookahead prefetching Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy, Chris Wilkerson, Zeshan Chishti |
Path confidence based lookahead prefetching Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
HARE: Hardware accelerator for regular expressions Vaibhav Gogte, Aasheesh Kolli, Michael J. Cafarella, Loris D'Antoni, Thomas F. Wenisch |
HARE: Hardware accelerator for regular expressions Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Continuous shape shifting: Enabling loop co-optimization via near-free dynamic code rewriting Animesh Jain, Michael A. Laurenzano, Lingjia Tang, Jason Mars |
Continuous shape shifting: Enabling loop co-optimization via near-free dynamic code rewriting Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints Yu Ji, Youhui Zhang, Shuangchen Li, Ping Chi, Cihang Jiang, Peng Qu, Yuan Xie, Wenguang Chen |
NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems Hadi Asghari Moghaddam, Young Hoon Son, Jung Ho Ahn, Nam Sung Kim |
Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
CANDY: Enabling coherent DRAM caches for multi-node systems Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi |
CANDY: Enabling coherent DRAM caches for multi-node systems Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
vDNN: Virtualized deep neural networks for scalable, memory-efficient neural network design Minsoo Rhu, Natalia Gimelshein, Jason Clemons, Arslan Zulfiqar, Stephen W. Keckler |
vDNN: Virtualized deep neural networks for scalable, memory-efficient neural network design Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Cambricon-X: An accelerator for sparse neural networks Shijin Zhang, Zidong Du, Lei Zhang, Huiying Lan, Shaoli Liu, Ling Li, Qi Guo, Tianshi Chen, Yunji Chen |
Cambricon-X: An accelerator for sparse neural networks Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Dynamic error mitigation in NoCs using intelligent prediction techniques Dominic DiTomaso, Travis Boraten, Avinash Kodi, Ahmed Louri |
Dynamic error mitigation in NoCs using intelligent prediction techniques Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Ti-states: Processor power management in the temperature inversion region Yazhou Zu, Wei Huang, Indrani Paul, Vijay Janapa Reddi |
Ti-states: Processor power management in the temperature inversion region Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Radha Venkatagiri, Abdulrahman Mahmoud, Siva Kumar Sastry Hari, Sarita V. Adve |
Details |
Author Comments:
The Approxilyzer tool has been released and is located at https://cs.illinois.edu/approxilyzer.
Discussion Comments:
0
Sharing:
Research produced artifacts
Verification:
Authors have
verified
information
|
|
|
A cloud-scale acceleration architecture Adrian M. Caulfield, Eric S. Chung, Andrew Putnam, Hari Angepat, Jeremy Fowers, Michael Haselman, Stephen Heil, Matt Humphrey, Puneet Kaur, Joo-Young Kim, Daniel Lo, Todd Massengill, Kalin Ovtcharov, Michael Papamichael, Lisa Woods, Sitaram Lanka, Derek Chiou, Doug Burger |
A cloud-scale acceleration architecture Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Register sharing for equality prediction Arthur Perais, Fernando A. Endo, André Seznec |
Register sharing for equality prediction Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Manoj Alwani, Han Chen, Michael Ferdman, Peter Milder |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
CrystalBall: Statically analyzing runtime behavior via deep sequence learning Stephen Zekany, Daniel Rings, Nathan Harada, Michael A. Laurenzano, Lingjia Tang, Jason Mars |
CrystalBall: Statically analyzing runtime behavior via deep sequence learning Details |
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
|
NeSC: Self-virtualizing nested storage controller Yonatan Gottesman, Yoav Etsion |
NeSC: Self-virtualizing nested storage controller Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
A patch memory system for image processing and computer vision Jason Clemons, Chih-Chi Cheng, Iuri Frosio, Daniel R. Johnson, Stephen W. Keckler |
A patch memory system for image processing and computer vision Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Yang Hu, Tao Li |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Contention-based congestion management in large-scale networks Gwangsun Kim, Changhyun Kim, Jiyun Jeong, Mike Parker, John Kim |
Contention-based congestion management in large-scale networks Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures Jia Zhan, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Yuan Xie |
OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Improving energy efficiency of DRAM by exploiting half page row access Heonjae Ha, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz |
Improving energy efficiency of DRAM by exploiting half page row access Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
GRAPE: Minimizing energy for GPU applications with performance requirements Muhammad Husni Santriaji, Henry Hoffmann |
GRAPE: Minimizing energy for GPU applications with performance requirements Details |
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
|
Jump over ASLR: Attacking branch predictors to bypass ASLR Dmitry Evtyushkin, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh |
Jump over ASLR: Attacking branch predictors to bypass ASLR Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Efficient data supply for hardware accelerators with prefetching and access/execute decoupling Tao Chen, G. Edward Suh |
Efficient data supply for hardware accelerators with prefetching and access/execute decoupling Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Efficient kernel synthesis for performance portable programming Li-Wen Chang, Izzat El Hajj, Christopher I. Rodrigues, Juan Gómez-Luna, Wen-mei W. Hwu |
Efficient kernel synthesis for performance portable programming Details |
|
Author Comments:
Discussion Comments:
0
Sharing:
Not able to share produced artifacts
Verification:
Authors have
verified
information
|
|
Data-centric execution of speculative parallel programs Mark C. Jeffrey, Suvinay Subramanian, Maleen Abeydeera, Joel S. Emer, Daniel Sánchez |
Data-centric execution of speculative parallel programs Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Zorua: A holistic approach to resource virtualization in GPUs Nandita Vijaykumar, Kevin Hsieh, Gennady Pekhimenko, Samira Manabi Khan, Ashish Shrestha, Saugata Ghose, Adwait Jog, Phillip B. Gibbons, Onur Mutlu |
Zorua: A holistic approach to resource virtualization in GPUs Details |
|
Author Comments:
Discussion Comments:
0
Sharing:
Not able to share produced artifacts
Verification:
Authors have
verified
information
|
|
Co-designing accelerators and SoC interfaces using gem5-Aladdin Yakun Sophia Shao, Sam Likun Xi, Vijayalakshmi Srinivasan, Gu-Yeon Wei, David M. Brooks |
Co-designing accelerators and SoC interfaces using gem5-Aladdin Details |
Author Comments:
Discussion Comments:
0
Sharing:
Research produced artifacts
Verification:
Authors have
verified
information
|
|
|
An ultra low-power hardware accelerator for automatic speech recognition Reza Yazdani, Albert Segura, Jose-Maria Arnau, Antonio González |
An ultra low-power hardware accelerator for automatic speech recognition Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert C. N. Pilawa-Podgurski, Ulya R. Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas |
Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs Naifeng Jing, Jianfei Wang, Fengfeng Fan, Wenkang Yu, Li Jiang, Chao Li, Xiaoyao Liang |
Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
KLAP: Kernel launch aggregation and promotion for optimizing dynamic parallelism Izzat El Hajj, Juan Gómez-Luna, Cheng Li, Li-Wen Chang, Dejan S. Milojicic, Wen-mei W. Hwu |
KLAP: Kernel launch aggregation and promotion for optimizing dynamic parallelism Details |
|
Author Comments:
Discussion Comments:
0
Sharing:
Not able to share produced artifacts
Verification:
Authors have
verified
information
|
|
Spectral profiling: Observer-effect-free profiling by monitoring EM emanations Nader Sehatbakhsh, Alireza Nazari, Alenka G. Zajic, Milos Prvulovic |
Spectral profiling: Observer-effect-free profiling by monitoring EM emanations Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Perceptron learning for reuse prediction Elvira Teran, Zhe Wang, Daniel A. Jiménez |
Perceptron learning for reuse prediction Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
SABRes: Atomic object reads for in-memory rack-scale computing Alexandros Daglis, Dmitrii Ustiugov, Stanko Novakovic, Edouard Bugnion, Babak Falsafi, Boris Grot |
SABRes: Atomic object reads for in-memory rack-scale computing Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Bridging the I/O performance gap for big data workloads: A new NVDIMM-based approach Renhai Chen, Zili Shao, Tao Li |
Bridging the I/O performance gap for big data workloads: A new NVDIMM-based approach Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Dictionary sharing: An efficient cache compression scheme for compressed caches Biswabandan Panda, André Seznec |
Dictionary sharing: An efficient cache compression scheme for compressed caches Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Keynotes: Internet of Things: History and hype, technology and policy Margaret Martonosi |
Keynotes: Internet of Things: History and hype, technology and policy Details |
|
Discussion Comments:
0
Verification:
Author has
not verified
information
|
|
Aasheesh Kolli, Jeff Rosen, Stephan Diestelhorst, Ali G. Saidi, Steven Pelley, Sihang Liu, Peter M. Chen, Thomas F. Wenisch |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
The microarchitecture of a real-time robot motion planning accelerator Sean Murray, William Floyd-Jones, Ying Qi, George Dimitri Konidaris, Daniel J. Sorin |
The microarchitecture of a real-time robot motion planning accelerator Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
MIMD synchronization on SIMT architectures Ahmed ElTantawy, Tor M. Aamodt |
MIMD synchronization on SIMT architectures Details |
Author Comments:
Please contact ahmede@ece.ubc.ca if you have any questions.
Discussion Comments:
0
Sharing:
Research produced artifacts
Verification:
Authors have
verified
information
|
|
|
Chainsaw: Von-neumann accelerators to leverage fused instruction chains Amirali Sharifian, Snehasish Kumar, Apala Guha, Arrvindh Shriraman |
Chainsaw: Von-neumann accelerators to leverage fused instruction chains Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Exploiting semantic commutativity in hardware speculation Guowei Zhang, Virginia Chiu, Daniel Sánchez |
Exploiting semantic commutativity in hardware speculation Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
The Bunker Cache for spatio-value approximation Joshua San Miguel, Jorge Albericio, Natalie D. Enright Jerger, Aamer Jaleel |
The Bunker Cache for spatio-value approximation Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Lazy release consistency for GPUs Johnathan Alsop, Marc S. Orr, Bradford M. Beckmann, David A. Wood |
Lazy release consistency for GPUs Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Redefining QoS and customizing the power management policy to satisfy individual mobile users Kaige Yan, Xingyao Zhang, Jingweijia Tan, Xin Fu |
Redefining QoS and customizing the power management policy to satisfy individual mobile users Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Concise loads and stores: The case for an asymmetric compute-memory architecture for approximation Animesh Jain, Parker Hill, Shih-Chieh Lin, Muneeb Khan, Md Enamul Haque, Michael A. Laurenzano, Scott A. Mahlke, Lingjia Tang, Jason Mars |
Concise loads and stores: The case for an asymmetric compute-memory architecture for approximation Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
From high-level deep neural models to FPGAs Hardik Sharma, Jongse Park, Divya Mahajan, Emmanuel Amaro, Joon Kyung Kim, Chenkai Shao, Asit Mishra, Hadi Esmaeilzadeh |
From high-level deep neural models to FPGAs Details |
Author Comments:
Discussion Comments:
0
Sharing:
Research produced artifacts
Verification:
Authors have
verified
information
|
|
|
Stripes: Bit-serial deep neural network computing Patrick Judd, Jorge Albericio, Tayler H. Hetherington, Tor M. Aamodt, Andreas Moshovos |
Stripes: Bit-serial deep neural network computing Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Graphicionado: A high-performance and energy-efficient accelerator for graph analytics Tae Jun Ham, Lisa Wu, Narayanan Sundaram, Nadathur Satish, Margaret Martonosi |
Graphicionado: A high-performance and energy-efficient accelerator for graph analytics Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Improving bank-level parallelism for irregular applications Xulong Tang, Mahmut T. Kandemir, Praveen Yedlapalli, Jagadish Kotra |
Improving bank-level parallelism for irregular applications Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Racer: TSO consistency via race detection Alberto Ros, Stefanos Kaxiras |
Racer: TSO consistency via race detection Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Evaluating programmable architectures for imaging and vision applications Artem Vasilyev, Nikhil Bhagdikar, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz |
Evaluating programmable architectures for imaging and vision applications Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
ReplayConfusion: Detecting cache-based covert channel attacks using record and replay Mengjia Yan, Yasser Shalabi, Josep Torrellas |
ReplayConfusion: Detecting cache-based covert channel attacks using record and replay Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
C3D: Mitigating the NUMA bottleneck via coherent DRAM caches Cheng-Chieh Huang, Rakesh Kumar, Marco Elver, Boris Grot, Vijay Nagarajan |
C3D: Mitigating the NUMA bottleneck via coherent DRAM caches Details |
Author Comments:
Discussion Comments:
0
Sharing:
Research produced artifacts
Verification:
Authors have
verified
information
|
|
|
PoisonIvy: Safe speculation for secure memory Tamara Silbergleit Lehman, Andrew D. Hilton, Benjamin C. Lee |
PoisonIvy: Safe speculation for secure memory Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Continuous runahead: Transparent hardware acceleration for memory intensive workloads Milad Hashemi, Onur Mutlu, Yale N. Patt |
Continuous runahead: Transparent hardware acceleration for memory intensive workloads Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Qingrui Liu, Changhee Jung, Dongyoon Lee, Devesh Tiwari |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
A unified memory network architecture for in-memory computing in commodity servers Jia Zhan, Itir Akgun, Jishen Zhao, Al Davis, Paolo Faraboschi, Yuangang Wang, Yuan Xie |
A unified memory network architecture for in-memory computing in commodity servers Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|