Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs

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Title:	Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs
Article URLs:	https://doi.org/10.1109/MICRO.2016.7783717 http://doi.ieeecomputersociety.org/10.1109/MICRO.2016.7783717 http://dl.acm.org/citation.cfm?id=3195655
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Authors:	Naifeng Jing	Shanghai Jiao Tong University, Advanced Computer Architecture Laboratory
	Jianfei Wang	Shanghai Jiao Tong University, Advanced Computer Architecture Laboratory
	Fengfeng Fan	Shanghai Jiao Tong University, Advanced Computer Architecture Laboratory
	Wenkang Yu	Shanghai Jiao Tong University, Advanced Computer Architecture Laboratory
	Li Jiang	Shanghai Jiao Tong University, Advanced Computer Architecture Laboratory
	Chao Li	Shanghai Jiao Tong University, Advanced Computer Architecture Laboratory
	Xiaoyao Liang	Shanghai Jiao Tong University, Advanced Computer Architecture Laboratory
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DBLP Key:	conf/micro/JingWFYJLL16
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IEEE/ACM International Symposium on Microarchitecture, MICRO 2016