C<sup>3</sup>D: Mitigating the NUMA bottleneck via coherent DRAM caches

Article Details
Title:	C³D: Mitigating the NUMA bottleneck via coherent DRAM caches
Article URLs:	https://doi.org/10.1109/MICRO.2016.7783739 http://doi.ieeecomputersociety.org/10.1109/MICRO.2016.7783739 http://dl.acm.org/citation.cfm?id=3195681
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Authors:	Cheng-Chieh Huang	University of Edinburgh, Institute of Computing Systems Architecture
	Rakesh Kumar	University of Edinburgh, Institute of Computing Systems Architecture
	Marco Elver	University of Edinburgh, Institute of Computing Systems Architecture
	Boris Grot	University of Edinburgh, Institute of Computing Systems Architecture
	Vijay Nagarajan	University of Edinburgh, Institute of Computing Systems Architecture
Sharing:	Research produced artifacts
Verification:	Authors have verified information
Artifact Evaluation Badge:	none
Artifact URLs:	https://github.com/icsa-caps/c3d-protocol
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DBLP Key:	conf/micro/HuangKEGN16
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IEEE/ACM International Symposium on Microarchitecture, MICRO 2016