IEEE International Symposium on High Performance Computer Architecture, HPCA 2018


Title/Authors Title Research Artifacts
[?] A research artifact is any by-product of a research project that is not directly included in the published research paper. In Computer Science research this is often source code and data sets, but it could also be media, documentation, inputs to proof assistants, shell-scripts to run experiments, etc.
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Secure DIMM: Moving ORAM Primitives Closer to Memory

Ali Shafiee, Rajeev Balasubramonian, Mohit Tiwari, Feifei Li

Secure DIMM: Moving ORAM Primitives Closer to Memory

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Perception-Oriented 3D Rendering Approximation for Modern Graphics Processors

Chenhao Xie, Xin Fu, Shuaiwen Song

Perception-Oriented 3D Rendering Approximation for Modern Graphics Processors

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Reliability-Aware Data Placement for Heterogeneous Memory Architecture

Manish Gupta, Vilas Sridharan, David Roberts, Andreas Prodromou, Ashish Venkat, Dean M. Tullsen, Rajesh K. Gupta

Reliability-Aware Data Placement for Heterogeneous Memory Architecture

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RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases

Peng Wang, Shuo Li, Guangyu Sun, Xiaoyang Wang, Yiran Chen, Hai Li, Jason Cong, Nong Xiao, Tao Zhang

RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases

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High-Performance GPU Transactional Memory via Eager Conflict Detection

Xiaowei Ren, Mieszko Lis

High-Performance GPU Transactional Memory via Eager Conflict Detection

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ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness

Dmitry Knyaginin, Vassilis Papaefstathiou, Per Stenström

ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness

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GraphP: Reducing Communication for PIM-Based Graph Processing with Efficient Data Partition

Mingxing Zhang, Youwei Zhuo, Chao Wang, Mingyu Gao, Yongwei Wu, Kang Chen, Christos Kozyrakis, Xuehai Qian

GraphP: Reducing Communication for PIM-Based Graph Processing with Efficient Data Partition

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Enabling Efficient Network Service Function Chain Deployment on Heterogeneous Server Platform

Yang Hu, Tao Li

Enabling Efficient Network Service Function Chain Deployment on Heterogeneous Server Platform

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In-Situ AI: Towards Autonomous and Incremental Deep Learning for IoT Systems

Mingcong Song, Kan Zhong, Jiaqi Zhang, Yang Hu, Duo Liu, Weigong Zhang, Jing Wang, Tao Li

In-Situ AI: Towards Autonomous and Incremental Deep Learning for IoT Systems

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iNPG: Accelerating Critical Section Access with In-network Packet Generation for NoC Based Many-Cores

Yuan Yao, Zhonghai Lu

iNPG: Accelerating Critical Section Access with In-network Packet Generation for NoC Based Many-Cores

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Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning

Scott Van Winkle, Avinash Karanth Kodi, Razvan C. Bunescu, Ahmed Louri

Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning

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Memory Hierarchy for Web Search

Grant Ayers, Jung Ho Ahn, Christos Kozyrakis, Parthasarathy Ranganathan

Memory Hierarchy for Web Search

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Don't Correct the Tags in a Cache, Just Check Their Hamming Distance from the Lookup Tag

Alex Gendler, Arkady Bramnik, Ariel Szapiro, Yiannakis Sazeides

Don't Correct the Tags in a Cache, Just Check Their Hamming Distance from the Lookup Tag

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Towards Efficient Microarchitectural Design for Accelerating Unsupervised GAN-Based Deep Learning

Mingcong Song, Jiaqi Zhang, Huixiang Chen, Tao Li

Towards Efficient Microarchitectural Design for Accelerating Unsupervised GAN-Based Deep Learning

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Lost in Abstraction: Pitfalls of Analyzing GPUs at the Intermediate Language Level

Anthony Gutierrez, Bradford M. Beckmann, Alexandru Dutu, Joseph Gross, Michael LeBeane, John Kalamatianos, Onur Kayiran, Matthew Poremba, Brandon Potter, Sooraj Puthoor, Matthew D. Sinclair, Mark Wyse, Jieming Yin, Xianwei Zhang, Akshay Jain, Timothy G. Rogers

Lost in Abstraction: Pitfalls of Analyzing GPUs at the Intermediate Language Level

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GPGPU Power Modeling for Multi-domain Voltage-Frequency Scaling

João Guerreiro, Aleksandar Ilic, Nuno Roma, Pedro Tomás

GPGPU Power Modeling for Multi-domain Voltage-Frequency Scaling

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Domino Temporal Data Prefetcher

Mohammad Bakhshalipour, Pejman Lotfi-Kamran, Hamid Sarbazi-Azad

Domino Temporal Data Prefetcher

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Steal but No Force: Efficient Hardware Undo+Redo Logging for Persistent Memory Systems

Matheus Ogleari, Ethan L. Miller, Jishen Zhao

Steal but No Force: Efficient Hardware Undo+Redo Logging for Persistent Memory Systems

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NACHOS: Software-Driven Hardware-Assisted Memory Disambiguation for Accelerators

Naveen Vedula, Arrvindh Shriraman, Snehasish Kumar, William N. Sumner

NACHOS: Software-Driven Hardware-Assisted Memory Disambiguation for Accelerators

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Comprehensive VM Protection Against Untrusted Hypervisor Through Retrofitted AMD Memory Encryption

Yuming Wu, Yutao Liu, Ruifeng Liu, Haibo Chen, Binyu Zang, Haibing Guan

Comprehensive VM Protection Against Untrusted Hypervisor Through Retrofitted AMD Memory Encryption

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GraphR: Accelerating Graph Processing Using ReRAM

Linghao Song, Youwei Zhuo, Xuehai Qian, Hai Helen Li, Yiran Chen

GraphR: Accelerating Graph Processing Using ReRAM

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Routerless Network-on-Chip

Fawaz Alazemi, Arash AziziMazreah, Bella Bose, Lizhong Chen

Routerless Network-on-Chip

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Enabling Fine-Grain Restricted Coset Coding Through Word-Level Compression for PCM

Seyed Mohammad Seyedzadeh, Alex K. Jones, Rami G. Melhem

Enabling Fine-Grain Restricted Coset Coding Through Word-Level Compression for PCM

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Crash Consistency in Encrypted Non-volatile Main Memory Systems

Sihang Liu, Aasheesh Kolli, Jinglei Ren, Samira Manabi Khan

Crash Consistency in Encrypted Non-volatile Main Memory Systems

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SmarCo: An Efficient Many-Core Processor for High-Throughput Applications in Datacenters

Dongrui Fan, Wenming Li, Xiaochun Ye, Da Wang, Hao Zhang, Zhimin Tang, Ninghui Sun

SmarCo: An Efficient Many-Core Processor for High-Throughput Applications in Datacenters

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Are Coherence Protocol States Vulnerable to Information Leakage?

Fan Yao, Milos Doroslovacki, Guru Venkataramani

Are Coherence Protocol States Vulnerable to Information Leakage?

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Reducing Data Transfer Energy by Exploiting Similarity within a Data Transaction

Donghyuk Lee, Mike O'Connor, Niladrish Chatterjee

Reducing Data Transfer Energy by Exploiting Similarity within a Data Transaction

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Power and Energy Characterization of an Open Source 25-Core Manycore Processor

Michael McKeown, Alexey Lavrov, Mohammad Shahrad, Paul J. Jackson, Yaosheng Fu, Jonathan Balkind, Tri M. Nguyen, Katie Lim, Yanqi Zhou, David Wentzlaff

Power and Energy Characterization of an Open Source 25-Core Manycore Processor

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Warp Scheduling for Fine-Grained Synchronization

Ahmed ElTantawy, Tor M. Aamodt

Warp Scheduling for Fine-Grained Synchronization

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Characterizing Resource Sensitivity of Database Workloads

Rathijit Sen, Karthik Ramachandra

Characterizing Resource Sensitivity of Database Workloads

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LATTE-CC: Latency Tolerance Aware Adaptive Cache Compression Management for Energy Efficient GPUs

Akhil Arunkumar, Shin-Ying Lee, Vignesh Soundararajan, Carole-Jean Wu

LATTE-CC: Latency Tolerance Aware Adaptive Cache Compression Management for Energy Efficient GPUs

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OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator

Subhankar Pal, Jonathan Beaumont, Dong-Hyeon Park, Aporva Amarnath, Siying Feng, Chaitali Chakrabarti, Hun-Seok Kim, David Blaauw, Trevor N. Mudge, Ronald G. Dreslinski

OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator

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HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness

Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu

HeatWatch: Improving 3D NAND Flash Memory Device Reliability by Exploiting Self-Recovery and Temperature Awareness

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Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks

Minsoo Rhu, Mike O'Connor, Niladrish Chatterjee, Jeff Pool, Youngeun Kwon, Stephen W. Keckler

Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks

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DUO: Exposing On-Chip Redundancy to Rank-Level ECC for High Reliability

Seong-Lyong Gong, Jungrae Kim, Sangkug Lym, Michael Sullivan, Howard David, Mattan Erez

DUO: Exposing On-Chip Redundancy to Rank-Level ECC for High Reliability

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Characterizing and Mitigating Output Reporting Bottlenecks in Spatial Automata Processing Architectures

Jack Wadden, Kevin Angstadt, Kevin Skadron

Characterizing and Mitigating Output Reporting Bottlenecks in Spatial Automata Processing Architectures

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GDP: Using Dataflow Properties to Accurately Estimate Interference-Free Performance at Runtime

Magnus Jahre, Lieven Eeckhout

GDP: Using Dataflow Properties to Accurately Estimate Interference-Free Performance at Runtime

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SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories

Gururaj Saileshwar, Prashant J. Nair, Prakash Ramrakhyani, Wendy Elsasser, Moinuddin K. Qureshi

SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories

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ERUCA: Efficient DRAM Resource Utilization and Resource Conflict Avoidance for Memory System Parallelism

Sangkug Lym, Heonjae Ha, Yongkee Kwon, Chun-Kai Chang, Jungrae Kim, Mattan Erez

ERUCA: Efficient DRAM Resource Utilization and Resource Conflict Avoidance for Memory System Parallelism

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Applied Machine Learning at Facebook: A Datacenter Infrastructure Perspective

Kim M. Hazelwood, Sarah Bird, David M. Brooks, Soumith Chintala, Utku Diril, Dmytro Dzhulgakov, Mohamed Fawzy, Bill Jia, Yangqing Jia, Aditya Kalro, James Law, Kevin Lee, Jason Lu, Pieter Noordhuis, Misha Smelyanskiy, Liang Xiong, Xiaodong Wang

Applied Machine Learning at Facebook: A Datacenter Infrastructure Perspective

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A Novel Register Renaming Technique for Out-of-Order Processors

Hamid Tabani, Jose-Maria Arnau, Jordi Tubella, Antonio González

A Novel Register Renaming Technique for Out-of-Order Processors

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The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices

Jeremie S. Kim, Minesh Patel, Hasan Hassan, Onur Mutlu

The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices

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Amdahl's Law in the Datacenter Era: A Market for Fair Processor Allocation

Seyed Majid Zahedi, Qiuyun Llull, Benjamin C. Lee

Amdahl's Law in the Datacenter Era: A Market for Fair Processor Allocation

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Searching for Potential gRNA Off-Target Sites for CRISPR/Cas9 Using Automata Processing Across Different Platforms

Chunkun Bo, Vinh Dang, Elaheh Sadredini, Kevin Skadron

Searching for Potential gRNA Off-Target Sites for CRISPR/Cas9 Using Automata Processing Across Different Platforms

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Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures

Sriseshan Srikanth, Paul G. Rabbat, Eric R. Hein, Bobin Deng, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank

Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures

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Efficient and Fair Multi-programming in GPUs via Effective Bandwidth Management

Haonan Wang, Fan Luo, Mohamed Ibrahim, Onur Kayiran, Adwait Jog

Efficient and Fair Multi-programming in GPUs via Effective Bandwidth Management

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RCoal: Mitigating GPU Timing Attack via Subwarp-Based Randomized Coalescing Techniques

Gurunath Kadam, Danfeng Zhang, Adwait Jog

RCoal: Mitigating GPU Timing Attack via Subwarp-Based Randomized Coalescing Techniques

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Architectural Support for Task Dependence Management with Flexible Software Scheduling

Emilio Castillo, Lluc Alvarez, Miquel Moretó, Marc Casas, Enrique Vallejo, José Luis Bosque, Ramón Beivide, Mateo Valero

Architectural Support for Task Dependence Management with Flexible Software Scheduling

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A Case for Packageless Processors

Saptadeep Pal, Daniel Petrisko, Adeel A. Bajwa, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar

A Case for Packageless Processors

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A Spot Capacity Market to Increase Power Infrastructure Utilization in Multi-tenant Data Centers

Mohammad A. Islam, Xiaoqi Ren, Shaolei Ren, Adam Wierman

A Spot Capacity Market to Increase Power Infrastructure Utilization in Multi-tenant Data Centers

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D-ORAM: Path-ORAM Delegation for Low Execution Interference on Cloud Servers with Untrusted Memory

Rujia Wang, Youtao Zhang, Jun Yang

D-ORAM: Path-ORAM Delegation for Low Execution Interference on Cloud Servers with Untrusted Memory

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Adaptive Memory Fusion: Towards Transparent, Agile Integration of Persistent Memory

Dongliang Xue, Chao Li, Linpeng Huang, Chentao Wu, Tianyou Li

Adaptive Memory Fusion: Towards Transparent, Agile Integration of Persistent Memory

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Amdahl's Law in Big Data Analytics: Alive and Kicking in TPCx-BB (BigBench)

Daniel Richins, Tahrina Ahmed, Russell M. Clapp, Vijay Janapa Reddi

Amdahl's Law in Big Data Analytics: Alive and Kicking in TPCx-BB (BigBench)

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KPart: A Hybrid Cache Partitioning-Sharing Technique for Commodity Multicores

Nosayba El-Sayed, Anurag Mukkara, Po-An Tsai, Harshad Kasture, Xiaosong Ma, Daniel Sánchez

KPart: A Hybrid Cache Partitioning-Sharing Technique for Commodity Multicores

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Wait of a Decade: Did SPEC CPU 2017 Broaden the Performance Horizon?

Reena Panda, Shuang Song, Joseph Dean, Lizy K. John

Wait of a Decade: Did SPEC CPU 2017 Broaden the Performance Horizon?

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Making Memristive Neural Network Accelerators Reliable

Ben Feinberg, Shibo Wang, Engin Ipek

Making Memristive Neural Network Accelerators Reliable

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PM3: Power Modeling and Power Management for Processing-in-Memory

Chao Zhang, Tong Meng, Guangyu Sun

PM3: Power Modeling and Power Management for Processing-in-Memory

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WIR: Warp Instruction Reuse to Minimize Repeated Computations in GPUs

Keunsoo Kim, Won Woo Ro

WIR: Warp Instruction Reuse to Minimize Repeated Computations in GPUs

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SIPT: Speculatively Indexed, Physically Tagged Caches

Tianhao Zheng, Haishan Zhu, Mattan Erez

SIPT: Speculatively Indexed, Physically Tagged Caches

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Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls

Hongwen Dai, Zhen Lin, Chao Li, Chen Zhao, Fei Wang, Nanning Zheng, Huiyang Zhou

Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls

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Record-Replay Architecture as a General Security Framework

Yasser Shalabi, Mengjia Yan, Nima Honarmand, Ruby B. Lee, Josep Torrellas

Record-Replay Architecture as a General Security Framework

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G-TSC: Timestamp Based Coherence for GPUs

Abdulaziz Tabbakh, Xuehai Qian, Murali Annavaram

G-TSC: Timestamp Based Coherence for GPUs

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