SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories

Article Details
Title:	SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories
Article URLs:	https://doi.org/10.1109/HPCA.2018.00046 http://doi.ieeecomputersociety.org/10.1109/HPCA.2018.00046
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Authors:	Gururaj Saileshwar	Georgia Institute of Technology
	Prashant J. Nair	IBM Research
	Prakash Ramrakhyani	ARM Research
	Wendy Elsasser	ARM Research
	Moinuddin K. Qureshi	Georgia Institute of Technology
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NSF Award Numbers:	1526798
DBLP Key:	conf/hpca/SaileshwarNREQ18
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IEEE International Symposium on High Performance Computer Architecture, HPCA 2018