Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures

Article Details
Title:	Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures
Article URLs:	https://doi.org/10.1109/HPCA.2018.00065 http://doi.ieeecomputersociety.org/10.1109/HPCA.2018.00065
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Authors:	Sriseshan Srikanth	Georgia Institute of Technology
	Paul G. Rabbat	Intel Corporation
	Eric R. Hein	Georgia Institute of Technology
	Bobin Deng	Georgia Institute of Technology
	Thomas M. Conte	Georgia Institute of Technology
	Erik DeBenedictis	Sandia National Laboratories
	Jeanine E. Cook	Sandia National Laboratories
	Michael P. Frank	Sandia National Laboratories
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DBLP Key:	conf/hpca/SrikanthRHDCDCF18
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IEEE International Symposium on High Performance Computer Architecture, HPCA 2018