ACM International Symposium on Physical Design, ISPD 2017


Title/Authors Title Research Artifacts
[?] A research artifact is any by-product of a research project that is not directly included in the published research paper. In Computer Science research this is often source code and data sets, but it could also be media, documentation, inputs to proof assistants, shell-scripts to run experiments, etc.
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Generalized Force Directed Relaxation with Optimal Regions and Its Applications to Circuit Placement

Yao-Wen Chang

Generalized Force Directed Relaxation with Optimal Regions and Its Applications to Circuit Placement

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CAD Opportunities with Hyper-Pipelining

Mahesh A. Iyer

CAD Opportunities with Hyper-Pipelining

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Deep Learning in the Enhanced Cloud

Eric Chung

Deep Learning in the Enhanced Cloud

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DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment

Jiaojiao Ou, Bei Yu, Xiaoqing Xu, Joydeep Mitra, Yibo Lin, David Z. Pan

DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment

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How Game Engines Can Inspire EDA Tools Development: A use case for an open-source physical design library

Tiago Fontana, Renan Netto, Vinicius S. Livramento, Chrystian Guth, Sheiny Almeida, Laércio Lima Pilla, José Luís Güntzel

How Game Engines Can Inspire EDA Tools Development: A use case for an open-source physical design library

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The Quest for The Ultimate Learning Machine

Pradeep Dubey

The Quest for The Ultimate Learning Machine

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Improving Detailed Routability and Pin Access with 3D Monolithic Standard Cells

Daohang Shi, Azadeh Davoodi

Improving Detailed Routability and Pin Access with 3D Monolithic Standard Cells

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Bilinear Lithography Hotspot Detection

Hang Zhang, Fengyuan Zhu, Haocheng Li, Evangeline F. Y. Young, Bei Yu

Bilinear Lithography Hotspot Detection

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Past, Present and Future of the Research

Satoshi Goto

Past, Present and Future of the Research

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Research Challenges in Security-Aware Physical Design

Ramesh Karri

Research Challenges in Security-Aware Physical Design

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Rsyn: An Extensible Physical Synthesis Framework

Guilherme Flach, Mateus Fogaça, Jucemar Monteiro, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis

Rsyn: An Extensible Physical Synthesis Framework

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Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond

Ilgweon Kang, Chung-Kuan Cheng

Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond

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100x Evolution of Video Codec Chips

Jinjia Zhou, Dajiang Zhou, Satoshi Goto

100x Evolution of Video Codec Chips

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Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits

Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun, David Z. Pan

Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits

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A Fast Incremental Cycle Ratio Algorithm

Gang Wu, Chris Chu

A Fast Incremental Cycle Ratio Algorithm

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Modern Challenges in Constructing Clocks

Charles J. Alpert

Modern Challenges in Constructing Clocks

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An Effective Timing-Driven Detailed Placement Algorithm for FPGAs

Shounak Dhar, Mahesh A. Iyer, Saurabh N. Adya, Love Singhal, Nikolay Rubanov, David Z. Pan

An Effective Timing-Driven Detailed Placement Algorithm for FPGAs

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Clock-Aware FPGA Placement Contest

Stephen Yang, Chandra Mulpuri, Sainath Reddy, Meghraj Kalase, Srinivasan Dasasathyan, Mehrdad E. Dehkordi, Marvin Tom, Rajat Aggarwal

Clock-Aware FPGA Placement Contest

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Physical Design Challenges and Innovations to Meet Power, Speed, and Area Scaling Trend

Lee-Chung Lu

Physical Design Challenges and Innovations to Meet Power, Speed, and Area Scaling Trend

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Interesting Problems in Physical Synthesis

Pei-Hsin Ho

Interesting Problems in Physical Synthesis

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Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning

Wei-Ting Jonas Chan, Pei-Hsin Ho, Andrew B. Kahng, Prashant Saxena

Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning

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iTimerM: Compact and Accurate Timing Macro Modeling for Efficient Hierarchical Timing Analysis

Pei-Yu Lee, Iris Hui-Ru Jiang, Ting-You Yang

iTimerM: Compact and Accurate Timing Macro Modeling for Efficient Hierarchical Timing Analysis

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Pin Accessibility-Driven Detailed Placement Refinement

Yixiao Ding, Chris Chu, Wai-Kei Mak

Pin Accessibility-Driven Detailed Placement Refinement

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Physical Design Considerations of One-level RRAM-based Routing Multiplexers

Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon

Physical Design Considerations of One-level RRAM-based Routing Multiplexers

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Technology Options for Beyond-CMOS

Ian Young

Technology Options for Beyond-CMOS

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The Spirit of in-house CAD Achieved by the Legend of Master "Prof. Goto" and his Apprentices

Yuichi Nakamura

The Spirit of in-house CAD Achieved by the Legend of Master "Prof. Goto" and his Apprentices

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Challenges and Opportunities: From Near-memory Computing to In-memory Computing

Soroosh Khoram, Yue Zha, Jialiang Zhang, Jing Li

Challenges and Opportunities: From Near-memory Computing to In-memory Computing

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Clock Tree Construction based on Arrival Time Constraints

Rickard Ewetz, Cheng-Kok Koh

Clock Tree Construction based on Arrival Time Constraints

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Automatic Cell Layout in the 7nm Era

Pascal Cremer, Stefan Hougardy, Jan Schneider, Jannik Silvanus

Automatic Cell Layout in the 7nm Era

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A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum Movement

Nima Karimpour Darav, Ismail S. Bustany, Andrew A. Kennings, Laleh Behjat

A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum Movement

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Pushing the boundaries of Moore's Law to transition from FPGA to All Programmable Platform

Ivo Bolsens

Pushing the boundaries of Moore's Law to transition from FPGA to All Programmable Platform

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