|
Generalized Force Directed Relaxation with Optimal Regions and Its Applications to Circuit Placement
Yao-Wen Chang
|
Generalized Force Directed Relaxation with Optimal Regions and Its Applications to Circuit Placement
Details
|
|
Verification:
Author has
not verified
information
|
|
CAD Opportunities with Hyper-Pipelining
Mahesh A. Iyer
|
CAD Opportunities with Hyper-Pipelining
Details
|
|
Verification:
Author has
not verified
information
|
|
Deep Learning in the Enhanced Cloud
Eric Chung
|
Deep Learning in the Enhanced Cloud
Details
|
|
Verification:
Author has
not verified
information
|
|
DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment
Jiaojiao Ou, Bei Yu, Xiaoqing Xu, Joydeep Mitra, Yibo Lin, David Z. Pan
|
DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment
Details
|
|
Verification:
Authors have
not verified
information
|
|
How Game Engines Can Inspire EDA Tools Development: A use case for an open-source physical design library
Tiago Fontana, Renan Netto, Vinicius S. Livramento, Chrystian Guth, Sheiny Almeida, Laércio Lima Pilla, José Luís Güntzel
|
How Game Engines Can Inspire EDA Tools Development: A use case for an open-source physical design library
Details
|
|
Verification:
Authors have
not verified
information
|
|
The Quest for The Ultimate Learning Machine
Pradeep Dubey
|
The Quest for The Ultimate Learning Machine
Details
|
|
Author Comments:
Sharing:
Not able to share produced artifacts
Verification:
Author has
verified
information
|
|
Improving Detailed Routability and Pin Access with 3D Monolithic Standard Cells
Daohang Shi, Azadeh Davoodi
|
Improving Detailed Routability and Pin Access with 3D Monolithic Standard Cells
Details
|
|
Verification:
Authors have
not verified
information
|
|
Bilinear Lithography Hotspot Detection
Hang Zhang, Fengyuan Zhu, Haocheng Li, Evangeline F. Y. Young, Bei Yu
|
Bilinear Lithography Hotspot Detection
Details
|
|
Verification:
Authors have
not verified
information
|
|
Past, Present and Future of the Research
Satoshi Goto
|
Past, Present and Future of the Research
Details
|
|
Verification:
Author has
not verified
information
|
|
Research Challenges in Security-Aware Physical Design
Ramesh Karri
|
Research Challenges in Security-Aware Physical Design
Details
|
|
Verification:
Author has
not verified
information
|
|
Rsyn: An Extensible Physical Synthesis Framework
Guilherme Flach, Mateus Fogaça, Jucemar Monteiro, Marcelo O. Johann, Ricardo Augusto da Luz Reis
|
Rsyn: An Extensible Physical Synthesis Framework
Details
|
|
Verification:
Authors have
not verified
information
|
|
Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond
Ilgweon Kang, Chung-Kuan Cheng
|
Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond
Details
|
|
Verification:
Authors have
not verified
information
|
|
100x Evolution of Video Codec Chips
Jinjia Zhou, Dajiang Zhou, Satoshi Goto
|
100x Evolution of Video Codec Chips
Details
|
|
Verification:
Authors have
not verified
information
|
|
Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits
Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun, David Z. Pan
|
Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits
Details
|
|
Verification:
Authors have
not verified
information
|
|
A Fast Incremental Cycle Ratio Algorithm
Gang Wu, Chris Chu
|
A Fast Incremental Cycle Ratio Algorithm
Details
|
|
Verification:
Authors have
not verified
information
|
|
Modern Challenges in Constructing Clocks
Charles J. Alpert
|
Modern Challenges in Constructing Clocks
Details
|
|
Verification:
Author has
not verified
information
|
|
An Effective Timing-Driven Detailed Placement Algorithm for FPGAs
Shounak Dhar, Mahesh A. Iyer, Saurabh N. Adya, Love Singhal, Nikolay Rubanov, David Z. Pan
|
An Effective Timing-Driven Detailed Placement Algorithm for FPGAs
Details
|
|
Verification:
Authors have
not verified
information
|
|
Clock-Aware FPGA Placement Contest
Stephen Yang, Chandra Mulpuri, Sainath Reddy, Meghraj Kalase, Srinivasan Dasasathyan, Mehrdad E. Dehkordi, Marvin Tom, Rajat Aggarwal
|
Clock-Aware FPGA Placement Contest
Details
|
|
Verification:
Authors have
not verified
information
|
|
Physical Design Challenges and Innovations to Meet Power, Speed, and Area Scaling Trend
Lee-Chung Lu
|
Physical Design Challenges and Innovations to Meet Power, Speed, and Area Scaling Trend
Details
|
|
Verification:
Author has
not verified
information
|
|
Interesting Problems in Physical Synthesis
Pei-Hsin Ho
|
Interesting Problems in Physical Synthesis
Details
|
|
Verification:
Author has
not verified
information
|
|
Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning
Wei-Ting Jonas Chan, Pei-Hsin Ho, Andrew B. Kahng, Prashant Saxena
|
Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning
Details
|
|
Verification:
Authors have
not verified
information
|
|
iTimerM: Compact and Accurate Timing Macro Modeling for Efficient Hierarchical Timing Analysis
Pei-Yu Lee, Iris Hui-Ru Jiang, Ting-You Yang
|
iTimerM: Compact and Accurate Timing Macro Modeling for Efficient Hierarchical Timing Analysis
Details
|
|
Verification:
Authors have
not verified
information
|
|
Pin Accessibility-Driven Detailed Placement Refinement
Yixiao Ding, Chris Chu, Wai-Kei Mak
|
Pin Accessibility-Driven Detailed Placement Refinement
Details
|
|
Verification:
Authors have
not verified
information
|
|
Physical Design Considerations of One-level RRAM-based Routing Multiplexers
Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
|
Physical Design Considerations of One-level RRAM-based Routing Multiplexers
Details
|
|
Verification:
Authors have
not verified
information
|
|
Technology Options for Beyond-CMOS
Ian Young
|
Technology Options for Beyond-CMOS
Details
|
|
Verification:
Author has
not verified
information
|
|
The Spirit of in-house CAD Achieved by the Legend of Master "Prof. Goto" and his Apprentices
Yuichi Nakamura
|
The Spirit of in-house CAD Achieved by the Legend of Master "Prof. Goto" and his Apprentices
Details
|
|
Verification:
Author has
not verified
information
|
|
Challenges and Opportunities: From Near-memory Computing to In-memory Computing
Soroosh Khoram, Yue Zha, Jialiang Zhang, Jing Li
|
Challenges and Opportunities: From Near-memory Computing to In-memory Computing
Details
|
|
Verification:
Authors have
not verified
information
|
|
Clock Tree Construction based on Arrival Time Constraints
Rickard Ewetz, Cheng-Kok Koh
|
Clock Tree Construction based on Arrival Time Constraints
Details
|
|
Verification:
Authors have
not verified
information
|
|
Automatic Cell Layout in the 7nm Era
Pascal Cremer, Stefan Hougardy, Jan Schneider, Jannik Silvanus
|
Automatic Cell Layout in the 7nm Era
Details
|
|
Verification:
Authors have
not verified
information
|
|
A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum Movement
Nima Karimpour Darav, Ismail S. Bustany, Andrew A. Kennings, Laleh Behjat
|
A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum Movement
Details
|
|
Verification:
Authors have
not verified
information
|
|
Pushing the boundaries of Moore's Law to transition from FPGA to All Programmable Platform
Ivo Bolsens
|
Pushing the boundaries of Moore's Law to transition from FPGA to All Programmable Platform
Details
|
|
Verification:
Author has
not verified
information
|