| Title: |
Clock-Aware FPGA Placement Contest |
| Article URLs: |
|
| Alternative Article URLs: |
|
| Authors: |
Stephen Yang |
-
Xilinx Inc. 2100 Logic Drive San Jose, CA 95124
|
| Chandra Mulpuri |
-
Xilinx Inc. 2100 Logic Drive San Jose, CA 95124
|
| Sainath Reddy |
-
Xilinx Inc. 2100 Logic Drive San Jose, CA 95124
|
| Meghraj Kalase |
-
Xilinx Inc. 2100 Logic Drive San Jose, CA 95124
|
| Srinivasan Dasasathyan |
-
Xilinx Inc. 2100 Logic Drive San Jose, CA 95124
|
| Mehrdad E. Dehkordi |
-
Xilinx Inc. 2100 Logic Drive San Jose, CA 95124
|
| Marvin Tom |
-
Xilinx Inc. 2100 Logic Drive San Jose, CA 95124
|
| Rajat Aggarwal |
-
Xilinx Inc. 2100 Logic Drive San Jose, CA 95124
|
| Sharing: |
Unknown
|
| Verification: |
Authors have
not verified
information
|
| Artifact Evaluation Badge: |
none
|
| Artifact URLs: |
|
| Artifact Correspondence Email Addresses: |
|
| NSF Award Numbers: |
|
| DBLP Key: |
conf/ispd/YangMRKDDTA17
|
| Author Comments: |
|