An Effective Timing-Driven Detailed Placement Algorithm for FPGAs

Article Details
Title:	An Effective Timing-Driven Detailed Placement Algorithm for FPGAs
Article URLs:	https://doi.org/10.1145/3036669.3036682
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Authors:	Shounak Dhar	University of Texas at Austin
	Mahesh A. Iyer	Intel Corporation
	Saurabh N. Adya	Intel Corporation
	Love Singhal	Intel Corporation
	Nikolay Rubanov	Intel Corporation
	David Z. Pan	University of Texas at Austin
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DBLP Key:	conf/ispd/DharIASRP17
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ACM International Symposium on Physical Design, ISPD 2017