| Title/Authors | Title | Research Artifacts
[?] A research
artifact is any by-product of a research project that is not
directly included in the published research paper. In Computer
Science research this is often source code and data sets, but
it could also be media, documentation, inputs to proof
assistants, shell-scripts to run experiments, etc.
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A Case Study on Achieving Fair Data Age Distribution in Vehicular Communications Xinhai Zhang, Xinwu Song, Lei Feng, Lei Chen, Martin Törngren |
A Case Study on Achieving Fair Data Age Distribution in Vehicular Communications Details |
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TimerShield: Protecting High-Priority Tasks from Low-Priority Timer Interference (Outstanding Paper) Pratyush Patel, Manohar Vanga, Björn B. Brandenburg |
TimerShield: Protecting High-Priority Tasks from Low-Priority Timer Interference (Outstanding Paper) Details |
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Benchmark Generation for Timing Analysis Peter Wägemann, Tobias Distler, Christian Eichler, Wolfgang Schröder-Preikschat |
Benchmark Generation for Timing Analysis Details |
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Zhuoqun Cheng, Richard West, Ying Ye |
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Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform Matthias Becker, Borislav Nikolic, Dakshina Dasari, Benny Akesson, Vincent Nélis, Moris Behnam, Thomas Nolte |
Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform Details |
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Work-in-Progress: Wireless Network Reconfiguration for Control Systems Wenchen Wang, Daniel Mossé, Jason G. Pickel, Daniel G. Cole |
Work-in-Progress: Wireless Network Reconfiguration for Control Systems Details |
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A Reliable and Predictable Scratchpad-centric OS for Multi-core Embedded Systems Rohan Tabish, Renato Mancuso, Saud Wasly, Sujit S. Phatak, Rodolfo Pellizzoni, Marco Caccamo |
A Reliable and Predictable Scratchpad-centric OS for Multi-core Embedded Systems Details |
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Demo Abstract: Bounding Deadline Misses for Weakly-Hard Real-Time Systems Designed in CAPELLA Rafik Henia, L. Roux, Nicolas Sordon, Zain Alabedin Haj Hammadeh, Rolf Ernst, Sophie Quinton |
Demo Abstract: Bounding Deadline Misses for Weakly-Hard Real-Time Systems Designed in CAPELLA Details |
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Allowing Shared Libraries While Supporting Hardware Isolation in Multicore Real-Time Systems Namhoon Kim, Micaiah Chisholm, Nathan Otterness, James H. Anderson, F. Donelson Smith |
Allowing Shared Libraries While Supporting Hardware Isolation in Multicore Real-Time Systems Details |
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Distributed Dynamic Packet Scheduling for Handling Disturbances in Real-Time Wireless Networks Tianyu Zhang, Tao Gong, Chuancai Gu, Huayi Ji, Song Han, Qingxu Deng, Xiaobo Sharon Hu |
Distributed Dynamic Packet Scheduling for Handling Disturbances in Real-Time Wireless Networks Details |
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Revising Measurement-Based Probabilistic Timing Analysis Luca Santinelli, Fabrice Guet, Jérôme Morio |
Revising Measurement-Based Probabilistic Timing Analysis Details |
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Scope-Aware Useful Cache Block Analysis for Data Cache Related Preemption Delay Wei Zhang, Fan Gong, Lei Ju, Nan Guan, Zhiping Jia |
Scope-Aware Useful Cache Block Analysis for Data Cache Related Preemption Delay Details |
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Real-Time Fine Grained Occupancy Estimation Using Depth Sensors on ARM Embedded Platforms Sirajum Munir, Ripudaman Singh Arora, Craig Hesling, Juncheng Li, Jonathan Francis, Charles Shelton, Christopher Martin, Anthony Rowe, Mario Berges |
Real-Time Fine Grained Occupancy Estimation Using Depth Sensors on ARM Embedded Platforms Details |
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S. Shriram, Raghavendra Barkur, P. Joshua, B. Shanthibhushan |
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Periodic Task Mining in Embedded System Traces Oleg Iegorov, Reinier Torres, Sebastian Fischmeister |
Periodic Task Mining in Embedded System Traces Details |
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Pulsar: A Wireless Propagation-Aware Clock Synchronization Platform Adwait Dongare, Patrick Lazik, Niranjini Rajagopal, Anthony Rowe |
Pulsar: A Wireless Propagation-Aware Clock Synchronization Platform Details |
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vCAT: Dynamic Cache Management Using CAT Virtualization Meng Xu, Linh Thi Xuan Phan, Xuan Phan, Hyon-Young Choi, Insup Lee |
vCAT: Dynamic Cache Management Using CAT Virtualization Details |
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Christian Dietrich, Peter Wägemann, Peter Ulbrich, Daniel Lohmann |
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Work-in-Progress: Cross-Layer Real-Time Scheduling for Wireless Control System Wenchen Wang, Daniel Mossé, Jason G. Pickel, Daniel G. Cole |
Work-in-Progress: Cross-Layer Real-Time Scheduling for Wireless Control System Details |
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Mitra Nasri, Björn B. Brandenburg |
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Work-In-Progress: Protecting Real-Time GPU Applications on Integrated CPU-GPU SoC Platforms Waqar Ali, Heechul Yun |
Work-In-Progress: Protecting Real-Time GPU Applications on Integrated CPU-GPU SoC Platforms Details |
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A full version of this paper is being developed.
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Predictable Cache Coherence for Multi-core Real-Time Systems Mohamed Hassan, Anirudh M. Kaushik, Hiren D. Patel |
Predictable Cache Coherence for Multi-core Real-Time Systems Details |
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Efficient Latency Guarantees for Mixed-Criticality Networks-on-Chip Sebastian Tobuschat, Rolf Ernst |
Efficient Latency Guarantees for Mixed-Criticality Networks-on-Chip Details |
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Tao Gong, Huayi Ji, Song Han, Tianyu Zhang, Chuancai Gu, Xiaobo Sharon Hu, Mark Nixon |
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Juanjuan Wang, Hongan Wang |
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Work-in-Progress: Reducing Cache Conflicts via Interrupts and BUNDLE Scheduling Corey Tessler, Gedare Bloom, Nathan Fisher |
Work-in-Progress: Reducing Cache Conflicts via Interrupts and BUNDLE Scheduling Details |
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Timing-Anomaly Free Dynamic Scheduling of Task-Based Parallel Applications Petros Voudouris, Per Stenström, Risat Pathan |
Timing-Anomaly Free Dynamic Scheduling of Task-Based Parallel Applications Details |
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An Evaluation of the NVIDIA TX1 for Supporting Real-Time Computer-Vision Workloads Nathan Otterness, Ming Yang, Sarah Rust, Eunbyung Park, James H. Anderson, F. Donelson Smith, Alexander C. Berg, Shige Wang |
An Evaluation of the NVIDIA TX1 for Supporting Real-Time Computer-Vision Workloads Details |
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Demo Abstract: Co-simulation Framework for Autonomous Driving Systems with MATLAB/Simulink Shota Tokunaga, Takuya Azumi |
Demo Abstract: Co-simulation Framework for Autonomous Driving Systems with MATLAB/Simulink Details |
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A Requests Bundling DRAM Controller for Mixed-Criticality Systems Danlu Guo, Rodolfo Pellizzoni |
A Requests Bundling DRAM Controller for Mixed-Criticality Systems Details |
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Work-in-Progress: Utilization Based Schedulability Analysis for Wireless Sensor-Actuator Networks Dali Ismail, Mahbubur Rahman, Venkata P. Modekurthy, Abusayeed Saifullah |
Work-in-Progress: Utilization Based Schedulability Analysis for Wireless Sensor-Actuator Networks Details |
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Parcus: Energy-Aware and Robust Parallelization of AUTOSAR Legacy Applications Sebastian Kehr, Eduardo Quiñones, Dominik Langen, Bert Böddeker, Günter Schäfer |
Parcus: Energy-Aware and Robust Parallelization of AUTOSAR Legacy Applications Details |
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QoS-Aware Flash Memory Controller Bryan Suk Kim, Sang Lyul Min |
QoS-Aware Flash Memory Controller Details |
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EPC Enacted: Integration in an Industrial Toolbox and Use against a Railway Application Enrico Mezzetti, Mikel Fernández, Alen Bardizbanyan, Irune Agirre, Jaume Abella, Tullio Vardanega, Francisco J. Cazorla |
EPC Enacted: Integration in an Industrial Toolbox and Use against a Railway Application Details |
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Artifacts touch commercial products or third party IPs
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Demo Abstract: Tooling Support for Benchmarking Timing Analysis Christian Eichler, Peter Wägemann, Tobias Distler, Wolfgang Schröder-Preikschat |
Demo Abstract: Tooling Support for Benchmarking Timing Analysis Details |
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Probabilistic Real-Time Guarantees: There Is Life Beyond the i.i.d. Assumption (Outstanding Paper) Bernardo Villalba Frias, Luigi Palopoli, Luca Abeni, Daniele Fontanelli |
Probabilistic Real-Time Guarantees: There Is Life Beyond the i.i.d. Assumption (Outstanding Paper) Details |
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Yin Yan, Karthik Dantu, Steven Y. Ko, Jan Vitek, Lukasz Ziarek |
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Anand Bhat, Soheil Samii, Ragunathan Rajkumar |
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Valid Application of EVT in Timing Analysis by Randomising Execution Time Measurements George Lima, Iain Bate |
Valid Application of EVT in Timing Analysis by Randomising Execution Time Measurements Details |
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Synchronization Quality of IEEE 802.1AS in Large-Scale Industrial Automation Networks Marina Gutiérrez, Wilfried Steiner, Radu Dobrin, Sasikumar Punnekkat |
Synchronization Quality of IEEE 802.1AS in Large-Scale Industrial Automation Networks Details |
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