Work-in-Progress: FPGA Implementation of Synchronous Serial Interface for Hardware in Loop Simulation

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Title:	Work-in-Progress: FPGA Implementation of Synchronous Serial Interface for Hardware in Loop Simulation
Article URLs:	https://doi.org/10.1109/RTAS.2017.28 http://doi.ieeecomputersociety.org/10.1109/RTAS.2017.28
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Authors:	S. Shriram	ABB Bangalore, India GISPL Bangalore, India DMDR Dept Bangalore, India
	Raghavendra Barkur	ABB Bangalore, India GISPL Bangalore, India DMDR Dept. Bangalore, India
	P. Joshua	ABB Bangalore, India GISPL Bangalore, India DMDR Dept Bangalore, India
	B. Shanthibhushan	ABB Bangalore, India GISPL Bangalore, India DMDR Dept Bangalore, India
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DBLP Key:	conf/rtas/ShriramBJS17
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IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2017