IEEE/ACM Intl. Conf. on Parallel Architectures and Compilation Techniques, PACT 2017


Title/Authors Title Research Artifacts
[?] A research artifact is any by-product of a research project that is not directly included in the published research paper. In Computer Science research this is often source code and data sets, but it could also be media, documentation, inputs to proof assistants, shell-scripts to run experiments, etc.
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POSTER: Location-Aware Computation Mapping for Manycore Processors

Orhan Kislal, Jagadish Kotra, Xulong Tang, Mahmut Taylan Kandemir, Myoungsoo Jung

POSTER: Location-Aware Computation Mapping for Manycore Processors

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Sthira: A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency

Raghavendra Pradyumna Pothukuchi, Amin Ansari, Bhargava Gopireddy, Josep Torrellas

Sthira: A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency

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Lightweight Provenance Service for High-Performance Computing

Dong Dai, Yong Chen, Philip H. Carns, John Jenkins, Robert B. Ross

Lightweight Provenance Service for High-Performance Computing

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Introspective Computing

Karl Taht, Rajeev Balasubramonian

Introspective Computing

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Proxy Benchmarks for Emerging Big-Data Workloads

Reena Panda, Lizy Kurian John

Proxy Benchmarks for Emerging Big-Data Workloads

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POSTER: Bridge the Gap Between Neural Networks and Neuromorphic Hardware

Yu Ji, Youhui Zhang, Wenguang Chen, Yuan Xie

POSTER: Bridge the Gap Between Neural Networks and Neuromorphic Hardware

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POSTER: NUMA-Aware Power Management for Chip Multiprocessors

Changmin Ahn, Camilo A. Celis Guzman, Bernhard Egger

POSTER: NUMA-Aware Power Management for Chip Multiprocessors

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A Generalized Framework for Automatic Scripting Language Parallelization

Taewook Oh, Stephen R. Beard, Nick P. Johnson, Sergiy Popovych, David I. August

A Generalized Framework for Automatic Scripting Language Parallelization

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Graphie: Large-Scale Asynchronous Graph Traversals on Just a GPU

Wei Han, Daniel Mawhirter, Bo Wu, Matthew Buland

Graphie: Large-Scale Asynchronous Graph Traversals on Just a GPU

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Performance Improvement via Always-Abort HTM

Joseph Izraelevitz, Lingxiang Xiang, Michael L. Scott

Performance Improvement via Always-Abort HTM

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POSTER: Exploiting Approximations for Energy/Quality Tradeoffs in Service-Based Applications

Liu Liu, Sibren Isaacman, Abhishek Bhattacharjee, Ulrich Kremer

POSTER: Exploiting Approximations for Energy/Quality Tradeoffs in Service-Based Applications

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POSTER: DaQueue: A Data-Aware Work-Queue Design for GPGPUs

Ya-Shuai Lü, Libo Huang, Li Shen

POSTER: DaQueue: A Data-Aware Work-Queue Design for GPGPUs

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An Ultra Low-Power Hardware Accelerator for Acoustic Scoring in Speech Recognition

Hamid Tabani, Jose-Maria Arnau, Jordi Tubella, Antonio González

An Ultra Low-Power Hardware Accelerator for Acoustic Scoring in Speech Recognition

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Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries

Amro Awad, Arkaprava Basu, Sergey Blagodurov, Yan Solihin, Gabriel H. Loh

Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries

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SAM: Optimizing Multithreaded Cores for Speculative Parallelism

Maleen Abeydeera, Suvinay Subramanian, Mark C. Jeffrey, Joel S. Emer, Daniel Sánchez

SAM: Optimizing Multithreaded Cores for Speculative Parallelism

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End-to-End Deep Learning of Optimization Heuristics

Chris Cummins, Pavlos Petoumenos, Zheng Wang, Hugh Leather

End-to-End Deep Learning of Optimization Heuristics

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A GPU-Friendly Skiplist Algorithm

Nurit Moscovici, Nachshon Cohen, Erez Petrank

A GPU-Friendly Skiplist Algorithm

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POSTER: Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls

Hongwen Dai, Zhen Lin, Chao Li, Chen Zhao, Fei Wang, Nanning Zheng, Huiyang Zhou

POSTER: Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls

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DRUT: An Efficient Turbo Boost Solution via Load Balancing in Decoupled Look-Ahead Architecture

Raj Parihar, Michael C. Huang

DRUT: An Efficient Turbo Boost Solution via Load Balancing in Decoupled Look-Ahead Architecture

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Architecting a Novel Hybrid Cache with Low Energy

Jiacong He, Joseph Callenes-Sloan

Architecting a Novel Hybrid Cache with Low Energy

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Redesigning Go's Built-In Map to Support Concurrent Operations

Louis Jenkins, Tingzhe Zhou, Michael F. Spear

Redesigning Go's Built-In Map to Support Concurrent Operations

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Transparent Dual Memory Compression Architecture

Seikwon Kim, Seonyoung Lee, Taehoon Kim, Jaehyuk Huh

Transparent Dual Memory Compression Architecture

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POSTER: Improving NUMA System Efficiency with a Utilization-Based Co-scheduling

Younghyun Cho, Camilo A. Celis Guzman, Bernhard Egger

POSTER: Improving NUMA System Efficiency with a Utilization-Based Co-scheduling

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DrMP: Mixed Precision-Aware DRAM for High Performance Approximate and Precise Computing

XianWei Zhang, Youtao Zhang, Bruce R. Childers, Jun Yang

DrMP: Mixed Precision-Aware DRAM for High Performance Approximate and Precise Computing

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POSTER: Improving Datacenter Efficiency Through Partitioning-Aware Scheduling

Harshad Kasture, Xu Ji, Nosayba El-Sayed, Nathan Beckmann, Xiaosong Ma, Daniel Sánchez

POSTER: Improving Datacenter Efficiency Through Partitioning-Aware Scheduling

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RCU-HTM: Combining RCU with HTM to Implement Highly Efficient Concurrent Binary Search Trees

Dimitrios Siakavaras, Konstantinos Nikas, Georgios I. Goumas, Nectarios Koziris

RCU-HTM: Combining RCU with HTM to Implement Highly Efficient Concurrent Binary Search Trees

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Efficient Checkpointing of Loop-Based Codes for Non-volatile Main Memory

Hussein Elnawawy, Mohammad Alshboul, James Tuck, Yan Solihin

Efficient Checkpointing of Loop-Based Codes for Non-volatile Main Memory

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Leeway: Addressing Variability in Dead-Block Prediction for Last-Level Caches

Priyank Faldu, Boris Grot

Leeway: Addressing Variability in Dead-Block Prediction for Last-Level Caches

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POSTER: BigBus: A Scalable Optical Interconnect

Eldhose Peter, Janibul Bashir, Smruti R. Sarangi

POSTER: BigBus: A Scalable Optical Interconnect

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POSTER: Putting the G back into GPU/CPU Systems Research

Andreas Sembrant, Trevor E. Carlson, Erik Hagersten, David Black-Schaffer

POSTER: Putting the G back into GPU/CPU Systems Research

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POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory Accelerators

Swagath Venkataramani, Jungwook Choi, Vijayalakshmi Srinivasan, Kailash Gopalakrishnan, Leland Chang

POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory Accelerators

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POSTER: Cutting the Fat: Speeding Up RBM for Fast Deep Learning Through Generalized Redundancy Elimination

Lin Ning, Randall Pittman, Xipeng Shen

POSTER: Cutting the Fat: Speeding Up RBM for Fast Deep Learning Through Generalized Redundancy Elimination

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POSTER: Application-Driven Near-Data Processing for Similarity Search

Vincent T. Lee, Amrita Mazumdar, Carlo C. del Mundo, Armin Alaghi, Luis Ceze, Mark Oskin

POSTER: Application-Driven Near-Data Processing for Similarity Search

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Application Clustering Policies to Address System Fairness with Intel's Cache Allocation Technology

Vicent Selfa, Julio Sahuquillo, Lieven Eeckhout, Salvador Petit, María Engracia Gómez

Application Clustering Policies to Address System Fairness with Intel's Cache Allocation Technology

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POSTER: Statement Reordering to Alleviate Register Pressure for Stencils on GPUs

Prashant Singh Rawat, Aravind Sukumaran-Rajam, Atanas Rountev, Fabrice Rastello, Louis-Noël Pouchet, P. Sadayappan

POSTER: Statement Reordering to Alleviate Register Pressure for Stencils on GPUs

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SuperGraph-SLP Auto-Vectorization

Vasileios Porpodas

SuperGraph-SLP Auto-Vectorization

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Nexus: A New Approach to Replication in Distributed Shared Caches

Po-An Tsai, Nathan Beckmann, Daniel Sánchez

Nexus: A New Approach to Replication in Distributed Shared Caches

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MultiGraph: Efficient Graph Processing on GPUs

Changwan Hong, Aravind Sukumaran-Rajam, Jinsung Kim, P. Sadayappan

MultiGraph: Efficient Graph Processing on GPUs

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Multilayer Compute Resource Management with Robust Control Theory

Raghavendra Pradyumna Pothukuchi, Sweta Yamini Pothukuchi, Petros G. Voulgaris, Josep Torrellas

Multilayer Compute Resource Management with Robust Control Theory

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In-memory Data Flow Processor

Daichi Fujiki, Scott A. Mahlke, Reetuparna Das

In-memory Data Flow Processor

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POSTER: Elastic Reconfiguration for Heterogeneous NoCs with BiNoCHS

Amirhossein Mirhosseini, Mohammad Sadrosadati, Behnaz Soltani, Hamid Sarbazi-Azad, Thomas F. Wenisch

POSTER: Elastic Reconfiguration for Heterogeneous NoCs with BiNoCHS

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Large Scale Data Clustering Using Memristive k-Median Computation

Yomi Karthik Rupesh, Mahdi Nazm Bojnordi

Large Scale Data Clustering Using Memristive k-Median Computation

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POSTER: BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU Workloads

Yuxi Liu, Xia Zhao, Zhibin Yu, Zhenlin Wang, Xiaolin Wang, Yingwei Luo, Lieven Eeckhout

POSTER: BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU Workloads

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Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation

Yu-Ping Liu, Ding-Yong Hong, Jan-Jan Wu, Sheng-Yu Fu, Wei-Chung Hsu

Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation

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Cache Automaton: Repurposing Caches for Automata Processing

Arun Subramaniyan, Jingcheng Wang, Ezhil R. M. Balasubramanian, David Blaauw, Dennis Sylvester, Reetuparna Das

Cache Automaton: Repurposing Caches for Automata Processing

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A DSL for Performance Orchestration

Thiago Santos Faria Xavier Teixeira, David Padua, William Gropp

A DSL for Performance Orchestration

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POSTER: Bridging the Gap Between Deep Learning and Sparse Matrix Format Selection

Yue Zhao, Jiajia Li, Chunhua Liao, Xipeng Shen

POSTER: Bridging the Gap Between Deep Learning and Sparse Matrix Format Selection

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POSTER: The Liberation Day of Nondeterministic Programs

Enrico Armenio Deiana, Vincent St-Amour, Peter A. Dinda, Nikos Hardavellas, Simone Campanoni

POSTER: The Liberation Day of Nondeterministic Programs

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Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility

Sizhuo Zhang, Muralidaran Vijayaraghavan, Arvind

Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility

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Near-Memory Address Translation

Javier Picorel, Djordje Jevdjic, Babak Falsafi

Near-Memory Address Translation

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