| Title/Authors | Title | Research Artifacts
[?] A research
artifact is any by-product of a research project that is not
directly included in the published research paper. In Computer
Science research this is often source code and data sets, but
it could also be media, documentation, inputs to proof
assistants, shell-scripts to run experiments, etc.
|
Details |
|---|
|
POSTER: Location-Aware Computation Mapping for Manycore Processors Orhan Kislal, Jagadish Kotra, Xulong Tang, Mahmut Taylan Kandemir, Myoungsoo Jung |
POSTER: Location-Aware Computation Mapping for Manycore Processors Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Raghavendra Pradyumna Pothukuchi, Amin Ansari, Bhargava Gopireddy, Josep Torrellas |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Lightweight Provenance Service for High-Performance Computing Dong Dai, Yong Chen, Philip H. Carns, John Jenkins, Robert B. Ross |
Lightweight Provenance Service for High-Performance Computing Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Karl Taht, Rajeev Balasubramonian |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Proxy Benchmarks for Emerging Big-Data Workloads Reena Panda, Lizy Kurian John |
Proxy Benchmarks for Emerging Big-Data Workloads Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
POSTER: Bridge the Gap Between Neural Networks and Neuromorphic Hardware Yu Ji, Youhui Zhang, Wenguang Chen, Yuan Xie |
POSTER: Bridge the Gap Between Neural Networks and Neuromorphic Hardware Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
POSTER: NUMA-Aware Power Management for Chip Multiprocessors Changmin Ahn, Camilo A. Celis Guzman, Bernhard Egger |
POSTER: NUMA-Aware Power Management for Chip Multiprocessors Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
A Generalized Framework for Automatic Scripting Language Parallelization Taewook Oh, Stephen R. Beard, Nick P. Johnson, Sergiy Popovych, David I. August |
A Generalized Framework for Automatic Scripting Language Parallelization Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Graphie: Large-Scale Asynchronous Graph Traversals on Just a GPU Wei Han, Daniel Mawhirter, Bo Wu, Matthew Buland |
Graphie: Large-Scale Asynchronous Graph Traversals on Just a GPU Details |
Artifacts for some papers are reviewed by an artifact evaluation, reproducibility,
or similarly named committee. This is one such paper that passed review.
Artifact evaluation badge awarded
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Performance Improvement via Always-Abort HTM Joseph Izraelevitz, Lingxiang Xiang, Michael L. Scott |
Performance Improvement via Always-Abort HTM Details |
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
|
POSTER: Exploiting Approximations for Energy/Quality Tradeoffs in Service-Based Applications Liu Liu, Sibren Isaacman, Abhishek Bhattacharjee, Ulrich Kremer |
POSTER: Exploiting Approximations for Energy/Quality Tradeoffs in Service-Based Applications Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
POSTER: DaQueue: A Data-Aware Work-Queue Design for GPGPUs Ya-Shuai Lü, Libo Huang, Li Shen |
POSTER: DaQueue: A Data-Aware Work-Queue Design for GPGPUs Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
An Ultra Low-Power Hardware Accelerator for Acoustic Scoring in Speech Recognition Hamid Tabani, Jose-Maria Arnau, Jordi Tubella, Antonio González |
An Ultra Low-Power Hardware Accelerator for Acoustic Scoring in Speech Recognition Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries Amro Awad, Arkaprava Basu, Sergey Blagodurov, Yan Solihin, Gabriel H. Loh |
Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
SAM: Optimizing Multithreaded Cores for Speculative Parallelism Maleen Abeydeera, Suvinay Subramanian, Mark C. Jeffrey, Joel S. Emer, Daniel Sánchez |
SAM: Optimizing Multithreaded Cores for Speculative Parallelism Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
End-to-End Deep Learning of Optimization Heuristics Chris Cummins, Pavlos Petoumenos, Zheng Wang, Hugh Leather |
End-to-End Deep Learning of Optimization Heuristics Details |
Artifacts for some papers are reviewed by an artifact evaluation, reproducibility,
or similarly named committee. This is one such paper that passed review.
Artifact evaluation badge awarded
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
A GPU-Friendly Skiplist Algorithm Nurit Moscovici, Nachshon Cohen, Erez Petrank |
A GPU-Friendly Skiplist Algorithm Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
POSTER: Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls Hongwen Dai, Zhen Lin, Chao Li, Chen Zhao, Fei Wang, Nanning Zheng, Huiyang Zhou |
POSTER: Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
DRUT: An Efficient Turbo Boost Solution via Load Balancing in Decoupled Look-Ahead Architecture Raj Parihar, Michael C. Huang |
DRUT: An Efficient Turbo Boost Solution via Load Balancing in Decoupled Look-Ahead Architecture Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Architecting a Novel Hybrid Cache with Low Energy Jiacong He, Joseph Callenes-Sloan |
Architecting a Novel Hybrid Cache with Low Energy Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Redesigning Go's Built-In Map to Support Concurrent Operations Louis Jenkins, Tingzhe Zhou, Michael F. Spear |
Redesigning Go's Built-In Map to Support Concurrent Operations Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Transparent Dual Memory Compression Architecture Seikwon Kim, Seonyoung Lee, Taehoon Kim, Jaehyuk Huh |
Transparent Dual Memory Compression Architecture Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
POSTER: Improving NUMA System Efficiency with a Utilization-Based Co-scheduling Younghyun Cho, Camilo A. Celis Guzman, Bernhard Egger |
POSTER: Improving NUMA System Efficiency with a Utilization-Based Co-scheduling Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
DrMP: Mixed Precision-Aware DRAM for High Performance Approximate and Precise Computing XianWei Zhang, Youtao Zhang, Bruce R. Childers, Jun Yang |
DrMP: Mixed Precision-Aware DRAM for High Performance Approximate and Precise Computing Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
POSTER: Improving Datacenter Efficiency Through Partitioning-Aware Scheduling Harshad Kasture, Xu Ji, Nosayba El-Sayed, Nathan Beckmann, Xiaosong Ma, Daniel Sánchez |
POSTER: Improving Datacenter Efficiency Through Partitioning-Aware Scheduling Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
RCU-HTM: Combining RCU with HTM to Implement Highly Efficient Concurrent Binary Search Trees Dimitrios Siakavaras, Konstantinos Nikas, Georgios I. Goumas, Nectarios Koziris |
RCU-HTM: Combining RCU with HTM to Implement Highly Efficient Concurrent Binary Search Trees Details |
Artifacts for some papers are reviewed by an artifact evaluation, reproducibility,
or similarly named committee. This is one such paper that passed review.
Artifact evaluation badge awarded
|
Author Comments:
Discussion Comments:
0
Sharing:
Research produced artifacts
Verification:
Authors have
verified
information
|
|
Efficient Checkpointing of Loop-Based Codes for Non-volatile Main Memory Hussein Elnawawy, Mohammad A. Alshboul, James Tuck, Yan Solihin |
Efficient Checkpointing of Loop-Based Codes for Non-volatile Main Memory Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Leeway: Addressing Variability in Dead-Block Prediction for Last-Level Caches Priyank Faldu, Boris Grot |
Leeway: Addressing Variability in Dead-Block Prediction for Last-Level Caches Details |
Author Comments:
Discussion Comments:
0
Sharing:
Research produced artifacts
Verification:
Authors have
verified
information
|
|
|
POSTER: BigBus: A Scalable Optical Interconnect Eldhose Peter, Janibul Bashir, Smruti R. Sarangi |
POSTER: BigBus: A Scalable Optical Interconnect Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
POSTER: Putting the G back into GPU/CPU Systems Research Andreas Sembrant, Trevor E. Carlson, Erik Hagersten, David Black-Schaffer |
POSTER: Putting the G back into GPU/CPU Systems Research Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Swagath Venkataramani, Jungwook Choi, Vijayalakshmi Srinivasan, Kailash Gopalakrishnan, Leland Chang |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Lin Ning, Randall Pittman, Xipeng Shen |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
POSTER: Application-Driven Near-Data Processing for Similarity Search Vincent T. Lee, Amrita Mazumdar, Carlo C. del Mundo, Armin Alaghi, Luis Ceze, Mark Oskin |
POSTER: Application-Driven Near-Data Processing for Similarity Search Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Application Clustering Policies to Address System Fairness with Intel's Cache Allocation Technology Vicent Selfa, Julio Sahuquillo, Lieven Eeckhout, Salvador Petit, María Engracia Gómez |
Application Clustering Policies to Address System Fairness with Intel's Cache Allocation Technology Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
POSTER: Statement Reordering to Alleviate Register Pressure for Stencils on GPUs Prashant Singh Rawat, Aravind Sukumaran-Rajam, Atanas Rountev, Fabrice Rastello, Louis-Noël Pouchet, P. Sadayappan |
POSTER: Statement Reordering to Alleviate Register Pressure for Stencils on GPUs Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
SuperGraph-SLP Auto-Vectorization Vasileios Porpodas |
SuperGraph-SLP Auto-Vectorization Details |
Artifacts for some papers are reviewed by an artifact evaluation, reproducibility,
or similarly named committee. This is one such paper that passed review.
Artifact evaluation badge awarded
|
Discussion Comments:
0
Verification:
Author has
not verified
information
|
|
Nexus: A New Approach to Replication in Distributed Shared Caches Po-An Tsai, Nathan Beckmann, Daniel Sánchez |
Nexus: A New Approach to Replication in Distributed Shared Caches Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
MultiGraph: Efficient Graph Processing on GPUs Changwan Hong, Aravind Sukumaran-Rajam, Jinsung Kim, P. Sadayappan |
MultiGraph: Efficient Graph Processing on GPUs Details |
Artifacts for some papers are reviewed by an artifact evaluation, reproducibility,
or similarly named committee. This is one such paper that passed review.
Artifact evaluation badge awarded
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Multilayer Compute Resource Management with Robust Control Theory Raghavendra Pradyumna Pothukuchi, Sweta Yamini Pothukuchi, Petros G. Voulgaris, Josep Torrellas |
Multilayer Compute Resource Management with Robust Control Theory Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Daichi Fujiki, Scott A. Mahlke, Reetuparna Das |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
POSTER: Elastic Reconfiguration for Heterogeneous NoCs with BiNoCHS Amirhossein Mirhosseini, Mohammad Sadrosadati, Behnaz Soltani, Hamid Sarbazi-Azad, Thomas F. Wenisch |
POSTER: Elastic Reconfiguration for Heterogeneous NoCs with BiNoCHS Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Large Scale Data Clustering Using Memristive k-Median Computation Yomi Karthik Rupesh, Mahdi Nazm Bojnordi |
Large Scale Data Clustering Using Memristive k-Median Computation Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
POSTER: BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU Workloads Yuxi Liu, Xia Zhao, Zhibin Yu, Zhenlin Wang, Xiaolin Wang, Yingwei Luo, Lieven Eeckhout |
POSTER: BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU Workloads Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation Yu-Ping Liu, Ding-Yong Hong, Jan-Jan Wu, Sheng-Yu Fu, Wei-Chung Hsu |
Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Cache Automaton: Repurposing Caches for Automata Processing Arun Subramaniyan, Jingcheng Wang, Ezhil R. M. Balasubramanian, David T. Blaauw, Dennis Sylvester, Reetuparna Das |
Cache Automaton: Repurposing Caches for Automata Processing Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
A DSL for Performance Orchestration Thiago Santos Faria Xavier Teixeira, David A. Padua, William Gropp |
A DSL for Performance Orchestration Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
POSTER: Bridging the Gap Between Deep Learning and Sparse Matrix Format Selection Yue Zhao, Jiajia Li, Chunhua Liao, Xipeng Shen |
POSTER: Bridging the Gap Between Deep Learning and Sparse Matrix Format Selection Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
POSTER: The Liberation Day of Nondeterministic Programs Enrico Armenio Deiana, Vincent St-Amour, Peter A. Dinda, Nikos Hardavellas, Simone Campanoni |
POSTER: The Liberation Day of Nondeterministic Programs Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility Sizhuo Zhang, Muralidaran Vijayaraghavan, Arvind |
Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility Details |
|
Author Comments:
Discussion Comments:
0
Sharing:
Research produced no artifacts
Verification:
Authors have
verified
information
|
|
Near-Memory Address Translation Javier Picorel, Djordje Jevdjic, Babak Falsafi |
Near-Memory Address Translation Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|