POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory Accelerators

Article Details
Title:	POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory Accelerators
Article URLs:	https://doi.org/10.1109/PACT.2017.39 http://doi.ieeecomputersociety.org/10.1109/PACT.2017.39
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Authors:	Swagath Venkataramani	IBM T.J. Watson Research Center
	Jungwook Choi	IBM T.J. Watson Research Center
	Vijayalakshmi Srinivasan	IBM T.J. Watson Research Center
	Kailash Gopalakrishnan	IBM T.J. Watson Research Center
	Leland Chang	IBM T.J. Watson Research Center
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DBLP Key:	conf/IEEEpact/VenkataramaniCS17
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IEEE/ACM Intl. Conf. on Parallel Architectures and Compilation Techniques, PACT 2017