| Title/Authors | Title | Research Artifacts
[?] A research
artifact is any by-product of a research project that is not
directly included in the published research paper. In Computer
Science research this is often source code and data sets, but
it could also be media, documentation, inputs to proof
assistants, shell-scripts to run experiments, etc.
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POSTER: ξ-TAO: A Cache-centric Execution Model and Runtime for Deep Parallel Multicore Topologies Miquel Pericàs |
POSTER: ξ-TAO: A Cache-centric Execution Model and Runtime for Deep Parallel Multicore Topologies Details |
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A Static Cut-off for Task Parallel Programs Shintaro Iwasaki, Kenjiro Taura |
A Static Cut-off for Task Parallel Programs Details |
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EXCITE-VM: Extending the Virtual Memory System to Support Snapshot Isolation Transactions Heiner Litz, Benjamin Braun, David R. Cheriton |
EXCITE-VM: Extending the Virtual Memory System to Support Snapshot Isolation Transactions Details |
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OAWS: Memory Occlusion Aware Warp Scheduling Bin Wang, Yue Zhu, Weikuan Yu |
OAWS: Memory Occlusion Aware Warp Scheduling Details |
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Student Research Poster: Software Out-of-Order Execution for In-Order Architectures Kim-Anh Tran |
Student Research Poster: Software Out-of-Order Execution for In-Order Architectures Details |
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Bruno Bodin, Luigi Nardi, M. Zeeshan Zia, Harry Wagstaff, Govind Sreekar Shenoy, Murali Krishna Emani, John Mawer, Christos Kotselidis, Andy Nisbet, Mikel Luján, Björn Franke, Paul H. J. Kelly, Michael F. P. O'Boyle |
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Online Scalability Characterization of Data-Parallel Programs on Many Cores Younghyun Cho, Surim Oh, Bernhard Egger |
Online Scalability Characterization of Data-Parallel Programs on Many Cores Details |
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MicroSpec: Speculation-Centric Fine-Grained Parallelization for FSM Computations Junqiao Qiu, Zhijia Zhao, Bin Ren |
MicroSpec: Speculation-Centric Fine-Grained Parallelization for FSM Computations Details |
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Automatically Exploiting Implicit Pipeline Parallelism from Multiple Dependent Kernels for GPUs Gwangsun Kim, Jiyun Jeong, John Kim, Mark Stephenson |
Automatically Exploiting Implicit Pipeline Parallelism from Multiple Dependent Kernels for GPUs Details |
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Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities Ashutosh Pattnaik, Xulong Tang, Adwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Chita R. Das |
Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities Details |
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Combating the Reliability Challenge of GPU Register File at Low Supply Voltage Jingweijia Tan, Shuaiwen Leon Song, Kaige Yan, Xin Fu, Andrès Márquez, Darren J. Kerbyson |
Combating the Reliability Challenge of GPU Register File at Low Supply Voltage Details |
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Auto-tuning Spark Big Data Workloads on POWER8: Prediction-Based Dynamic SMT Threading Zhen Jia, Chao Xue, Guancheng Chen, Jianfeng Zhan, Lixin Zhang, Yonghua Lin, Peter Hofstee |
Auto-tuning Spark Big Data Workloads on POWER8: Prediction-Based Dynamic SMT Threading Details |
Artifacts for some papers are reviewed by an artifact evaluation, reproducibility,
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Vladislav Tartakovsky |
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Student Research Poster: From Processing-in-Memory to Processing-in-Storage Roman Kaplan |
Student Research Poster: From Processing-in-Memory to Processing-in-Storage Details |
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CAF: Core to Core Communication Acceleration Framework Yipeng Wang, Ren Wang, Andrew Herdrich, James Tsai, Yan Solihin |
CAF: Core to Core Communication Acceleration Framework Details |
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Student Research Poster: A Scalable General Purpose System for Large-Scale Graph Processing Jiawen Sun |
Student Research Poster: A Scalable General Purpose System for Large-Scale Graph Processing Details |
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Rahul Boyapati, Jiayi Huang, Ningyuan Wang, Kyung Hoon Kim, Ki Hwan Yum, Eun Jung Kim |
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Greater Performance and Better Efficiency: Predicated Execution has shown us the way Yale N. Patt |
Greater Performance and Better Efficiency: Predicated Execution has shown us the way Details |
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POSTER: hVISC: A Portable Abstraction for Heterogeneous Parallel Systems Prakalp Srivastava, Maria Kotsifakou, Matthew D. Sinclair, Rakesh Komuravelli, Vikram S. Adve, Sarita V. Adve |
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Resource Conscious Reuse-Driven Tiling for GPUs Prashant Singh Rawat, Changwan Hong, Mahesh Ravishankar, Vinod Grover, Louis-Noël Pouchet, Atanas Rountev, P. Sadayappan |
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Dibakar Gope, Mikko H. Lipasti |
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Scaling Data Analytics with Moore's Law Kunle Olukotun |
Scaling Data Analytics with Moore's Law Details |
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POSTER: An Optimization of Dataflow Architectures for Scientific Applications Xiaowei Shen, Xiaochun Ye, Xu Tan, Da Wang, Zhimin Zhang, Dongrui Fan, Zhimin Tang |
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Energy Aware Persistence: Reducing Energy Overheads of Memory-based Persistence in NVMs Sudarsun Kannan, Moinuddin K. Qureshi, Ada Gavrilovska, Karsten Schwan |
Energy Aware Persistence: Reducing Energy Overheads of Memory-based Persistence in NVMs Details |
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Student Research Poster: Network Controller Emulation on a Sidecore for Unmodified Virtual Machines Arthur Kiyanovski |
Student Research Poster: Network Controller Emulation on a Sidecore for Unmodified Virtual Machines Details |
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WearCore: A Core for Wearable Workloads Sanyam Mehta, Josep Torrellas |
WearCore: A Core for Wearable Workloads Details |
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Accelerating Linked-list Traversal Through Near-Data Processing Byungchul Hong, Gwangsun Kim, Jung Ho Ahn, Yongkee Kwon, Hongsik Kim, John Kim |
Accelerating Linked-list Traversal Through Near-Data Processing Details |
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POSTER: Easy PRAM-based High-Performance Parallel Programming with ICE Fady Ghanim, Rajeev Barua, Uzi Vishkin |
POSTER: Easy PRAM-based High-Performance Parallel Programming with ICE Details |
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POSTER: Hybrid Data Dependence Analysis for Loop Transformations Diogo Nunes Sampaio, Alain Ketterlin, Louis-Noël Pouchet, Fabrice Rastello |
POSTER: Hybrid Data Dependence Analysis for Loop Transformations Details |
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Optimizing Indirect Memory References with milk Vladimir Kiriansky, Yunming Zhang, Saman P. Amarasinghe |
Optimizing Indirect Memory References with milk Details |
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A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs Nitin Chugh, Vinay Vasista, Suresh Purini, Uday Bondhugula |
A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs Details |
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Mingcong Song, Yang Hu, Yunlong Xu, Chao Li, Huixiang Chen, Jingling Yuan, Tao Li |
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Reduction Drawing: Language Constructs and Polyhedral Compilation for Reductions on GPU Chandan Reddy, Michael Kruse, Albert Cohen |
Reduction Drawing: Language Constructs and Polyhedral Compilation for Reductions on GPU Details |
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Speculatively Exploiting Cross-Invocation Parallelism Jialu Huang, Prakash Prabhu, Thomas B. Jablin, Soumyadeep Ghosh, Sotiris Apostolakis, Jae W. Lee, David I. August |
Speculatively Exploiting Cross-Invocation Parallelism Details |
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Characterizing and Optimizing the Performance of Multithreaded Programs Under Interference Yong Zhao, Jia Rao, Qing Yi |
Characterizing and Optimizing the Performance of Multithreaded Programs Under Interference Details |
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Student Research Poster: Slack-Aware Shared Bandwidth Management in GPUs Saumay Dublish |
Student Research Poster: Slack-Aware Shared Bandwidth Management in GPUs Details |
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POSTER: An Integrated Vector-Scalar Design on an In-order ARM Core Milan Stanic, Oscar Palomar, Timothy Hayes, Ivan Ratkovic, Osman S. Unsal, Adrián Cristal, Mateo Valero |
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Sparso: Context-driven Optimizations of Sparse Linear Algebra Hongbo Rong, Jongsoo Park, Lingxiang Xiang, Todd A. Anderson, Mikhail Smelyanskiy |
Sparso: Context-driven Optimizations of Sparse Linear Algebra Details |
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POSTER: Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics Alberto Ros, Carl Leonardsson, Christos Sakalis, Stefanos Kaxiras |
POSTER: Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics Details |
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Big Data Analytics on Flash Storage with Accelerators Arvind |
Big Data Analytics on Flash Storage with Accelerators Details |
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POSTER: Firestorm: Operating Systems for Power-Constrained Architectures Sankaralingam Panneerselvam, Michael M. Swift |
POSTER: Firestorm: Operating Systems for Power-Constrained Architectures Details |
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Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling Paul Caheny, Marc Casas, Miquel Moretó, Hervé Gloaguen, Maxime Saintes, Eduard Ayguadé, Jesús Labarta, Mateo Valero |
Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling Details |
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Power Tuning HPC Jobs on Power-Constrained Systems Neha Gholkar, Frank Mueller, Barry Rountree |
Power Tuning HPC Jobs on Power-Constrained Systems Details |
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Andi Drebes, Antoniu Pop, Karine Heydemann, Albert Cohen, Nathalie Drach |
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POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware Kallia Chronaki, Miquel Moretó, Marc Casas, Alejandro Rico, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero |
POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware Details |
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POSTER: SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization Jee Ho Ryoo, Mitesh R. Meswani, Reena Panda, Lizy K. John |
POSTER: SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization Details |
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Tardis 2.0: Optimized Time Traveling Coherence for Relaxed Consistency Models Xiangyao Yu, Hongzhe Liu, Ethan Zou, Srinivas Devadas |
Tardis 2.0: Optimized Time Traveling Coherence for Relaxed Consistency Models Details |
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Tsung Tai Yeh, Amit Sabne, Putt Sakdhnagool, Rudolf Eigenmann, Timothy G. Rogers |
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Student Research Poster: A Low Complexity Cache Sharing Mechanism to Address System Fairness Vicent Selfa, Julio Sahuquillo, Salvador Petit, María Engracia Gómez |
Student Research Poster: A Low Complexity Cache Sharing Mechanism to Address System Fairness Details |
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Rinnegan: Efficient Resource Use in Heterogeneous Architectures Sankaralingam Panneerselvam, Michael M. Swift |
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μC-States: Fine-grained GPU Datapath Power Management Onur Kayiran, Adwait Jog, Ashutosh Pattnaik, Rachata Ausavarungnirun, Xulong Tang, Mahmut T. Kandemir, Gabriel H. Loh, Onur Mutlu, Chita R. Das |
μC-States: Fine-grained GPU Datapath Power Management Details |
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Florian Haas, Sebastian Weis, Theo Ungerer, Gilles Pokam, Youfeng Wu |
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Vectorization of Multibyte Floating Point Data Formats Andrew Anderson, David Gregg |
Vectorization of Multibyte Floating Point Data Formats Details |
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POSTER: Collective Dynamic Parallelism for Directive Based GPU Programming Languages and Compilers Guray Ozen, Eduard Ayguadé, Jesús Labarta |
POSTER: Collective Dynamic Parallelism for Directive Based GPU Programming Languages and Compilers Details |
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Fusion of Parallel Array Operations Mads Ruben Burgdorff Kristensen, Simon Andreas Frimann Lund, Troels Blum, James Avery |
Fusion of Parallel Array Operations Details |
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