| Title/Authors | Title | Research Artifacts
[?] A research
artifact is any by-product of a research project that is not
directly included in the published research paper. In Computer
Science research this is often source code and data sets, but
it could also be media, documentation, inputs to proof
assistants, shell-scripts to run experiments, etc.
|
Details |
|---|
|
All-Inclusive ECC: Thorough End-to-End Protection for Reliable Computer Memory Jungrae Kim, Michael B. Sullivan, Sangkug Lym, Mattan Erez |
All-Inclusive ECC: Thorough End-to-End Protection for Reliable Computer Memory Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Biscuit: A Framework for Near-Data Processing of Big Data Workloads Boncheol Gu, Andre S. Yoon, Duck-Ho Bae, Insoon Jo, Jinyoung Lee, Jonghyun Yoon, Jeong-Uk Kang, Moonsang Kwon, Chanho Yoon, Sangyeun Cho, Jaeheon Jeong, Duckhyun Chang |
Biscuit: A Framework for Near-Data Processing of Big Data Workloads Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators Brandon Reagen, Paul N. Whatmough, Robert Adolf, Saketh Rama, Hyunkwang Lee, Sae Kyu Lee, José Miguel Hernández-Lobato, Gu-Yeon Wei, David M. Brooks |
Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Efficient Synonym Filtering and Scalable Delayed Translation for Hybrid Virtual Caching Thomas Peyrin, Yu Sasaki, David Cunningham |
Efficient Synonym Filtering and Scalable Delayed Translation for Hybrid Virtual Caching Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Efficiently Scaling Out-of-Order Cores for Simultaneous Multithreading Faissal M. Sleiman, Thomas F. Wenisch |
Efficiently Scaling Out-of-Order Cores for Simultaneous Multithreading Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
XED: Exposing On-Die Error Detection Information for Strong Memory Reliability Prashant J. Nair, Vilas Sridharan, Moinuddin K. Qureshi |
XED: Exposing On-Die Error Detection Information for Strong Memory Reliability Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches Hsiang-Yun Cheng, Jishen Zhao, Jack Sampson, Mary Jane Irwin, Aamer Jaleel, Yu Lu, Yuan Xie |
LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Virtual Thread: Maximizing Thread-Level Parallelism beyond GPU Scheduling Limit Myung Kuk Yoon, Keunsoo Kim, Sangpil Lee, Won Woo Ro, Murali Annavaram |
Virtual Thread: Maximizing Thread-Level Parallelism beyond GPU Scheduling Limit Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Agile Paging: Exceeding the Best of Nested and Shadow Paging Jayneel Gandhi, Mark D. Hill, Michael M. Swift |
Agile Paging: Exceeding the Best of Nested and Shadow Paging Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Base-Victim Compression: An Opportunistic Cache Compression Architecture Jayesh Gaur, Alaa R. Alameldeen, Sreenivas Subramoney |
Base-Victim Compression: An Opportunistic Cache Compression Architecture Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Rescuing Uncorrectable Fault Patterns in On-Chip Memories through Error Pattern Transformation Henry Duwe, Xun Jian, Daniel Petrisko, Rakesh Kumar |
Rescuing Uncorrectable Fault Patterns in On-Chip Memories through Error Pattern Transformation Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars Ali Shafiee, Anirban Nag, Naveen Muralimanohar, Rajeev Balasubramonian, John Paul Strachan, Miao Hu, R. Stanley Williams, Vivek Srikumar |
ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars Details |
|
Author Comments:
Discussion Comments:
0
Sharing:
Research produced no artifacts
Verification:
Authors have
verified
information
|
|
Decoupling Loads for Nano-Instruction Set Computers Ziqiang Huang, Andrew D. Hilton, Benjamin C. Lee |
Decoupling Loads for Nano-Instruction Set Computers Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
EIE: Efficient Inference Engine on Compressed Deep Neural Network Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally |
EIE: Efficient Inference Engine on Compressed Deep Neural Network Details |
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
|
MITTS: Memory Inter-arrival Time Traffic Shaping Yanqi Zhou, David Wentzlaff |
MITTS: Memory Inter-arrival Time Traffic Shaping Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
ActivePointers: A Case for Software Address Translation on GPUs Sagi Shahar, Shai Bergman, Mark Silberstein |
ActivePointers: A Case for Software Address Translation on GPUs Details |
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
|
Opportunistic Competition Overhead Reduction for Expediting Critical Section in NoC Based CMPs Yuan Yao, Zhonghai Lu |
Opportunistic Competition Overhead Reduction for Expediting Critical Section in NoC Based CMPs Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Production-Run Software Failure Diagnosis via Adaptive Communication Tracking Mohammad Mejbah Ul Alam, Abdullah Muzahid |
Production-Run Software Failure Diagnosis via Adaptive Communication Tracking Details |
Author Comments:
Discussion Comments:
0
Sharing:
Research produced artifacts
Verification:
Authors have
verified
information
|
|
|
Joshua San Miguel, Natalie D. Enright Jerger |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Boosting Access Parallelism to PCM-Based Main Memory Mohammad Arjomand, Mahmut T. Kandemir, Anand Sivasubramaniam, Chita R. Das |
Boosting Access Parallelism to PCM-Based Main Memory Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Morpheus: Creating Application Objects Efficiently for Heterogeneous Computing Hung-Wei Tseng, Qianchen Zhao, Yuxiao Zhou, Mark Gahagan, Steven Swanson |
Morpheus: Creating Application Objects Efficiently for Heterogeneous Computing Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
PowerChop: Identifying and Managing Non-critical Units in Hybrid Processor Architectures Michael A. Laurenzano, Yunqi Zhang, Jiang Chen, Lingjia Tang, Jason Mars |
PowerChop: Identifying and Managing Non-critical Units in Hybrid Processor Architectures Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Cambricon: An Instruction Set Architecture for Neural Networks Shaoli Liu, Zidong Du, Jinhua Tao, Dong Han, Tao Luo, Yuan Xie, Yunji Chen, Tianshi Chen |
Cambricon: An Instruction Set Architecture for Neural Networks Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Towards Statistical Guarantees in Controlling Quality Tradeoffs for Approximate Acceleration Divya Mahajan, Amir Yazdanbakhsh, Jongse Park, Bradley Thwaites, Hadi Esmaeilzadeh |
Towards Statistical Guarantees in Controlling Quality Tradeoffs for Approximate Acceleration Details |
|
Author Comments:
Discussion Comments:
0
Sharing:
Research produced no artifacts
Verification:
Authors have
verified
information
|
|
LaPerm: Locality Aware Scheduler for Dynamic Parallelism on GPUs Jin Wang, Norm Rubin, Albert Sidelnik, Sudhakar Yalamanchili |
LaPerm: Locality Aware Scheduler for Dynamic Parallelism on GPUs Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Raghavendra Pradyumna Pothukuchi, Amin Ansari, Petros G. Voulgaris, Josep Torrellas |
Details |
|
Author Comments:
The paper describes the insights behind a new methodology and the technical report at http://iacoma.cs.uiuc.edu/iacoma-papers/mimoTR.pdf describes the detailed steps using MATLAB.
Discussion Comments:
0
Sharing:
Other
Verification:
Authors have
verified
information
|
|
Asymmetry-Aware Work-Stealing Runtimes Christopher Torng, Moyang Wang, Christopher Batten |
Asymmetry-Aware Work-Stealing Runtimes Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric Mingyu Gao, Christina Delimitrou, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Christos Kozyrakis |
DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Yunqi Zhang, David Meisner, Jason Mars, Lingjia Tang |
Details |
Author Comments:
Discussion Comments:
0
Sharing:
Research produced artifacts
Verification:
Authors have
verified
information
|
|
|
Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, Yuan Xie |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Kevin Hsieh, Eiman Ebrahimi, Gwangsun Kim, Niladrish Chatterjee, Mike O'Connor, Nandita Vijaykumar, Onur Mutlu, Stephen W. Keckler |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Efficient Synonym Filtering and Scalable Delayed Translation for Hybrid Virtual Caching Chang Hyun Park, Taekyung Heo, Jaehyuk Huh |
Efficient Synonym Filtering and Scalable Delayed Translation for Hybrid Virtual Caching Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
APRES: Improving Cache Efficiency by Exploiting Load Characteristics on GPUs Yunho Oh, Keunsoo Kim, Myung Kuk Yoon, Jong Hyun Park, Yongjun Park, Won Woo Ro, Murali Annavaram |
APRES: Improving Cache Efficiency by Exploiting Load Characteristics on GPUs Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems Hari Cherupalli, Rakesh Kumar, John Sartori |
Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Energy Efficient Architecture for Graph Analytics Accelerators Muhammet Mustafa Ozdal, Serif Yesil, Taemin Kim, Andrey Ayupov, John Greth, Steven M. Burns, Özcan Özturk |
Energy Efficient Architecture for Graph Analytics Accelerators Details |
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
|
Energy Efficient Data Encoding in DRAM Channels Exploiting Data Value Similarity Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim |
Energy Efficient Data Encoding in DRAM Channels Exploiting Data Value Similarity Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Short-Circuit Dispatch: Accelerating Virtual Machine Interpreters on Embedded Processors Channoh Kim, Sungmin Kim, Hyeon-Gyu Cho, Doo-Young Kim, Jaehyeok Kim, Young H. Oh, Hakbeom Jang, Jae W. Lee |
Short-Circuit Dispatch: Accelerating Virtual Machine Interpreters on Embedded Processors Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Back to the Future: Leveraging Belady's Algorithm for Improved Cache Replacement Akanksha Jain, Calvin Lin |
Back to the Future: Leveraging Belady's Algorithm for Improved Cache Replacement Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
ASIC Clouds: Specializing the Datacenter Ikuo Magaki, Moein Khazraee, Luis Vega Gutierrez, Michael Bedford Taylor |
ASIC Clouds: Specializing the Datacenter Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
CASH: Supporting IaaS Customers with a Sub-core Configurable Architecture Yanqi Zhou, Henry Hoffmann, David Wentzlaff |
CASH: Supporting IaaS Customers with a Sub-core Configurable Architecture Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Peak Efficiency Aware Scheduling for Highly Energy Proportional Servers Daniel Wong |
Peak Efficiency Aware Scheduling for Highly Energy Proportional Servers Details |
|
Discussion Comments:
0
Verification:
Author has
not verified
information
|
|
Cnvlutin: Ineffectual-Neuron-Free Deep Neural Network Computing Jorge Albericio, Patrick Judd, Tayler H. Hetherington, Tor M. Aamodt, Natalie D. Enright Jerger, Andreas Moshovos |
Cnvlutin: Ineffectual-Neuron-Free Deep Neural Network Computing Details |
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
|
Bit-Plane Compression: Transforming Data for Better Compression in Many-Core Architectures Jungrae Kim, Michael B. Sullivan, Esha Choukse, Mattan Erez |
Bit-Plane Compression: Transforming Data for Better Compression in Many-Core Architectures Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Dynamo: Facebook's Data Center-Wide Power Management System Qiang Wu, Qingyuan Deng, Lakshmi Ganesh, Chang-Hong Hsu, Yun Jin, Sanjeev Kumar, Bin Li, Justin Meza, Yee Jiun Song |
Dynamo: Facebook's Data Center-Wide Power Management System Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Qiumin Xu, Hyeran Jeon, Keunsoo Kim, Won Woo Ro, Murali Annavaram |
Details |
Author Comments:
Discussion Comments:
0
Sharing:
Research produced artifacts
Verification:
Authors have
verified
information
|
|
|
RedEye: Analog ConvNet Image Sensor Architecture for Continuous Mobile Vision Robert LiKamWa, Yunhui Hou, Yuan Gao, Mia Polansky, Lin Zhong |
RedEye: Analog ConvNet Image Sensor Architecture for Continuous Mobile Vision Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Dong-Wan Kim, Mattan Erez |
Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Future Vector Microprocessor Extensions for Data Aggregations Timothy Hayes, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Mateo Valero |
Future Vector Microprocessor Extensions for Data Aggregations Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs Lunkai Zhang, Brian Neely, Diana Franklin, Dmitri B. Strukov, Yuan Xie, Frederic T. Chong |
Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory Duckhwan Kim, Jaeha Kung, Sek M. Chai, Sudhakar Yalamanchili, Saibal Mukhopadhyay |
Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Power Attack Defense: Securing Battery-Backed Data Centers Chao Li, Zhenhua Wang, Xiaofeng Hou, Haopeng Chen, Xiaoyao Liang, Minyi Guo |
Power Attack Defense: Securing Battery-Backed Data Centers Details |
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
|
Automatic Generation of Efficient Accelerators for Reconfigurable Hardware David Koeplinger, Raghu Prabhakar, Yaqi Zhang, Christina Delimitrou, Christos Kozyrakis, Kunle Olukotun |
Automatic Generation of Efficient Accelerators for Reconfigurable Hardware Details |
Author Comments:
Discussion Comments:
0
Sharing:
Research produced artifacts
Verification:
Authors have
verified
information
|
|
|
Evaluation of an Analog Accelerator for Linear Algebra Yipeng Huang, Ning Guo, Mingoo Seok, Yannis P. Tsividis, Simha Sethumadhavan |
Evaluation of an Analog Accelerator for Linear Algebra Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
ARM Virtualization: Performance and Architectural Implications Christoffer Dall, Shih-Wei Li, Jin Tack Lim, Jason Nieh, Georgios Koloventzos |
ARM Virtualization: Performance and Architectural Implications Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Accelerating Dependent Cache Misses with an Enhanced Memory Controller Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, Yale N. Patt |
Accelerating Dependent Cache Misses with an Enhanced Memory Controller Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL Donggyu Kim, Adam M. Izraelevitz, Christopher Celio, Hokeun Kim, Brian Zimmer, Yunsup Lee, Jonathan Bachrach, Krste Asanovic |
Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
Accelerating Markov Random Field Inference Using Molecular Optical Gibbs Sampling Units Siyang Wang, Xiangyu Zhang, Yuxuan Li, Ramin Bashizade, Song Yang, Chris Dwyer, Alvin R. Lebeck |
Accelerating Markov Random Field Inference Using Molecular Optical Gibbs Sampling Units Details |
Discussion Comments:
0
Verification:
Authors have
not verified
information
|
|
|
Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks Yu-Hsin Chen, Joel S. Emer, Vivienne Sze |
Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks Details |
|
Discussion Comments:
0
Verification:
Authors have
not verified
information
|