ACM/IEEE International Symposium on Computer Architecture, ISCA 2016


Title/Authors Title Research Artifacts
[?] A research artifact is any by-product of a research project that is not directly included in the published research paper. In Computer Science research this is often source code and data sets, but it could also be media, documentation, inputs to proof assistants, shell-scripts to run experiments, etc.
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All-Inclusive ECC: Thorough End-to-End Protection for Reliable Computer Memory

Jungrae Kim, Michael Sullivan, Sangkug Lym, Mattan Erez

All-Inclusive ECC: Thorough End-to-End Protection for Reliable Computer Memory

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Biscuit: A Framework for Near-Data Processing of Big Data Workloads

Boncheol Gu, Andre S. Yoon, Duck-Ho Bae, Insoon Jo, Jinyoung Lee, Jonghyun Yoon, Jeong-Uk Kang, Moonsang Kwon, Chanho Yoon, Sangyeun Cho, Jaeheon Jeong, Duckhyun Chang

Biscuit: A Framework for Near-Data Processing of Big Data Workloads

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Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators

Brandon Reagen, Paul N. Whatmough, Robert Adolf, Saketh Rama, Hyunkwang Lee, Sae Kyu Lee, José Miguel Hernández-Lobato, Gu-Yeon Wei, David M. Brooks

Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators

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Efficient Synonym Filtering and Scalable Delayed Translation for Hybrid Virtual Caching

Chang Hyun Park, Taekyung Heo, Jaehyuk Huh

Efficient Synonym Filtering and Scalable Delayed Translation for Hybrid Virtual Caching

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Efficiently Scaling Out-of-Order Cores for Simultaneous Multithreading

Faissal M. Sleiman, Thomas F. Wenisch

Efficiently Scaling Out-of-Order Cores for Simultaneous Multithreading

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XED: Exposing On-Die Error Detection Information for Strong Memory Reliability

Prashant J. Nair, Vilas Sridharan, Moinuddin K. Qureshi

XED: Exposing On-Die Error Detection Information for Strong Memory Reliability

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LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches

Hsiang-Yun Cheng, Jishen Zhao, Jack Sampson, Mary Jane Irwin, Aamer Jaleel, Yu Lu, Yuan Xie

LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches

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Virtual Thread: Maximizing Thread-Level Parallelism beyond GPU Scheduling Limit

Myung Kuk Yoon, Keunsoo Kim, Sangpil Lee, Won Woo Ro, Murali Annavaram

Virtual Thread: Maximizing Thread-Level Parallelism beyond GPU Scheduling Limit

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Agile Paging: Exceeding the Best of Nested and Shadow Paging

Jayneel Gandhi, Mark D. Hill, Michael M. Swift

Agile Paging: Exceeding the Best of Nested and Shadow Paging

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Base-Victim Compression: An Opportunistic Cache Compression Architecture

Jayesh Gaur, Alaa R. Alameldeen, Sreenivas Subramoney

Base-Victim Compression: An Opportunistic Cache Compression Architecture

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Rescuing Uncorrectable Fault Patterns in On-Chip Memories through Error Pattern Transformation

Henry Duwe, Xun Jian, Daniel Petrisko, Rakesh Kumar

Rescuing Uncorrectable Fault Patterns in On-Chip Memories through Error Pattern Transformation

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ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars

Ali Shafiee, Anirban Nag, Naveen Muralimanohar, Rajeev Balasubramonian, John Paul Strachan, Miao Hu, R. Stanley Williams, Vivek Srikumar

ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars

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Decoupling Loads for Nano-Instruction Set Computers

Ziqiang Huang, Andrew D. Hilton, Benjamin C. Lee

Decoupling Loads for Nano-Instruction Set Computers

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EIE: Efficient Inference Engine on Compressed Deep Neural Network

Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally

EIE: Efficient Inference Engine on Compressed Deep Neural Network

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MITTS: Memory Inter-arrival Time Traffic Shaping

Yanqi Zhou, David Wentzlaff

MITTS: Memory Inter-arrival Time Traffic Shaping

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ActivePointers: A Case for Software Address Translation on GPUs

Sagi Shahar, Shai Bergman, Mark Silberstein

ActivePointers: A Case for Software Address Translation on GPUs

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Opportunistic Competition Overhead Reduction for Expediting Critical Section in NoC Based CMPs

Yuan Yao, Zhonghai Lu

Opportunistic Competition Overhead Reduction for Expediting Critical Section in NoC Based CMPs

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Production-Run Software Failure Diagnosis via Adaptive Communication Tracking

Mohammad Mejbah Ul Alam, Abdullah Muzahid

Production-Run Software Failure Diagnosis via Adaptive Communication Tracking

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The Anytime Automaton

Joshua San Miguel, Natalie D. Enright Jerger

The Anytime Automaton

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Boosting Access Parallelism to PCM-Based Main Memory

Mohammad Arjomand, Mahmut T. Kandemir, Anand Sivasubramaniam, Chita R. Das

Boosting Access Parallelism to PCM-Based Main Memory

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Morpheus: Creating Application Objects Efficiently for Heterogeneous Computing

Hung-Wei Tseng, Qianchen Zhao, Yuxiao Zhou, Mark Gahagan, Steven Swanson

Morpheus: Creating Application Objects Efficiently for Heterogeneous Computing

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PowerChop: Identifying and Managing Non-critical Units in Hybrid Processor Architectures

Michael A. Laurenzano, Yunqi Zhang, Jiang Chen, Lingjia Tang, Jason Mars

PowerChop: Identifying and Managing Non-critical Units in Hybrid Processor Architectures

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Cambricon: An Instruction Set Architecture for Neural Networks

Shaoli Liu, Zidong Du, Jinhua Tao, Dong Han, Tao Luo, Yuan Xie, Yunji Chen, Tianshi Chen

Cambricon: An Instruction Set Architecture for Neural Networks

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Towards Statistical Guarantees in Controlling Quality Tradeoffs for Approximate Acceleration

Divya Mahajan, Amir Yazdanbakhsh, Jongse Park, Bradley Thwaites, Hadi Esmaeilzadeh

Towards Statistical Guarantees in Controlling Quality Tradeoffs for Approximate Acceleration

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LaPerm: Locality Aware Scheduler for Dynamic Parallelism on GPUs

Jin Wang, Norm Rubin, Albert Sidelnik, Sudhakar Yalamanchili

LaPerm: Locality Aware Scheduler for Dynamic Parallelism on GPUs

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Using Multiple Input, Multiple Output Formal Control to Maximize Resource Efficiency in Architectures

Raghavendra Pradyumna Pothukuchi, Amin Ansari, Petros G. Voulgaris, Josep Torrellas

Using Multiple Input, Multiple Output Formal Control to Maximize Resource Efficiency in Architectures

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Author Comments: The paper describes the insights behind a new methodology and the technical report at http://iacoma.cs.uiuc.edu/iacoma-papers/mimoTR.pdf describes the detailed steps using MATLAB.
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Asymmetry-Aware Work-Stealing Runtimes

Christopher Torng, Moyang Wang, Christopher Batten

Asymmetry-Aware Work-Stealing Runtimes

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DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric

Mingyu Gao, Christina Delimitrou, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Christos Kozyrakis

DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric

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Treadmill: Attributing the Source of Tail Latency through Precise Load Testing and Statistical Inference

Yunqi Zhang, David Meisner, Jason Mars, Lingjia Tang

Treadmill: Attributing the Source of Tail Latency through Precise Load Testing and Statistical Inference

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PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory

Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, Yuan Xie

PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory

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Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems

Kevin Hsieh, Eiman Ebrahimi, Gwangsun Kim, Niladrish Chatterjee, Mike O'Connor, Nandita Vijaykumar, Onur Mutlu, Stephen W. Keckler

Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems

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Efficient Synonym Filtering and Scalable Delayed Translation for Hybrid Virtual Caching

Chang Hyun Park, Taekyung Heo, Jaehyuk Huh

Efficient Synonym Filtering and Scalable Delayed Translation for Hybrid Virtual Caching

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APRES: Improving Cache Efficiency by Exploiting Load Characteristics on GPUs

Yunho Oh, Keunsoo Kim, Myung Kuk Yoon, Jong Hyun Park, Yongjun Park, Won Woo Ro, Murali Annavaram

APRES: Improving Cache Efficiency by Exploiting Load Characteristics on GPUs

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Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems

Hari Cherupalli, Rakesh Kumar, John Sartori

Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems

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Energy Efficient Architecture for Graph Analytics Accelerators

Muhammet Mustafa Ozdal, Serif Yesil, Taemin Kim, Andrey Ayupov, John Greth, Steven M. Burns, Özcan Özturk

Energy Efficient Architecture for Graph Analytics Accelerators

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Energy Efficient Data Encoding in DRAM Channels Exploiting Data Value Similarity

Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim

Energy Efficient Data Encoding in DRAM Channels Exploiting Data Value Similarity

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Short-Circuit Dispatch: Accelerating Virtual Machine Interpreters on Embedded Processors

Channoh Kim, Sungmin Kim, Hyeon-Gyu Cho, Doo-Young Kim, Jaehyeok Kim, Young H. Oh, Hakbeom Jang, Jae W. Lee

Short-Circuit Dispatch: Accelerating Virtual Machine Interpreters on Embedded Processors

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Back to the Future: Leveraging Belady's Algorithm for Improved Cache Replacement

Akanksha Jain, Calvin Lin

Back to the Future: Leveraging Belady's Algorithm for Improved Cache Replacement

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ASIC Clouds: Specializing the Datacenter

Ikuo Magaki, Moein Khazraee, Luis Vega Gutierrez, Michael Bedford Taylor

ASIC Clouds: Specializing the Datacenter

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CASH: Supporting IaaS Customers with a Sub-core Configurable Architecture

Yanqi Zhou, Henry Hoffmann, David Wentzlaff

CASH: Supporting IaaS Customers with a Sub-core Configurable Architecture

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Peak Efficiency Aware Scheduling for Highly Energy Proportional Servers

Daniel Wong

Peak Efficiency Aware Scheduling for Highly Energy Proportional Servers

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Cnvlutin: Ineffectual-Neuron-Free Deep Neural Network Computing

Jorge Albericio, Patrick Judd, Tayler H. Hetherington, Tor M. Aamodt, Natalie D. Enright Jerger, Andreas Moshovos

Cnvlutin: Ineffectual-Neuron-Free Deep Neural Network Computing

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Bit-Plane Compression: Transforming Data for Better Compression in Many-Core Architectures

Jungrae Kim, Michael Sullivan, Esha Choukse, Mattan Erez

Bit-Plane Compression: Transforming Data for Better Compression in Many-Core Architectures

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Dynamo: Facebook's Data Center-Wide Power Management System

Qiang Wu, Qingyuan Deng, Lakshmi Ganesh, Chang-Hong Hsu, Yun Jin, Sanjeev Kumar, Bin Li, Justin Meza, Yee Jiun Song

Dynamo: Facebook's Data Center-Wide Power Management System

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Warped-Slicer: Efficient Intra-SM Slicing through Dynamic Resource Partitioning for GPU Multiprogramming

Qiumin Xu, Hyeran Jeon, Keunsoo Kim, Won Woo Ro, Murali Annavaram

Warped-Slicer: Efficient Intra-SM Slicing through Dynamic Resource Partitioning for GPU Multiprogramming

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RedEye: Analog ConvNet Image Sensor Architecture for Continuous Mobile Vision

Robert LiKamWa, Yunhui Hou, Yuan Gao, Mia Polansky, Lin Zhong

RedEye: Analog ConvNet Image Sensor Architecture for Continuous Mobile Vision

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RelaxFault Memory Repair

Dong-Wan Kim, Mattan Erez

RelaxFault Memory Repair

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Future Vector Microprocessor Extensions for Data Aggregations

Timothy Hayes, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Mateo Valero

Future Vector Microprocessor Extensions for Data Aggregations

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Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs

Lunkai Zhang, Brian Neely, Diana Franklin, Dmitri B. Strukov, Yuan Xie, Frederic T. Chong

Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs

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Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory

Duckhwan Kim, Jaeha Kung, Sek M. Chai, Sudhakar Yalamanchili, Saibal Mukhopadhyay

Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory

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Power Attack Defense: Securing Battery-Backed Data Centers

Chao Li, Zhenhua Wang, Xiaofeng Hou, Haopeng Chen, Xiaoyao Liang, Minyi Guo

Power Attack Defense: Securing Battery-Backed Data Centers

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Automatic Generation of Efficient Accelerators for Reconfigurable Hardware

David Koeplinger, Raghu Prabhakar, Yaqi Zhang, Christina Delimitrou, Christos Kozyrakis, Kunle Olukotun

Automatic Generation of Efficient Accelerators for Reconfigurable Hardware

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Evaluation of an Analog Accelerator for Linear Algebra

Yipeng Huang, Ning Guo, Mingoo Seok, Yannis P. Tsividis, Simha Sethumadhavan

Evaluation of an Analog Accelerator for Linear Algebra

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ARM Virtualization: Performance and Architectural Implications

Christoffer Dall, Shih-Wei Li, Jin Tack Lim, Jason Nieh, Georgios Koloventzos

ARM Virtualization: Performance and Architectural Implications

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Accelerating Dependent Cache Misses with an Enhanced Memory Controller

Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, Yale N. Patt

Accelerating Dependent Cache Misses with an Enhanced Memory Controller

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Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL

Donggyu Kim, Adam M. Izraelevitz, Christopher Celio, Hokeun Kim, Brian Zimmer, Yunsup Lee, Jonathan Bachrach, Krste Asanovic

Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL

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Accelerating Markov Random Field Inference Using Molecular Optical Gibbs Sampling Units

Siyang Wang, Xiangyu Zhang, Yuxuan Li, Ramin Bashizade, Song Yang, Chris Dwyer, Alvin R. Lebeck

Accelerating Markov Random Field Inference Using Molecular Optical Gibbs Sampling Units

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Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks

Yu-Hsin Chen, Joel S. Emer, Vivienne Sze

Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks

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