IEEE International Symposium on High Performance Computer Architecture, HPCA 2017


Title/Authors Title Research Artifacts
[?] A research artifact is any by-product of a research project that is not directly included in the published research paper. In Computer Science research this is often source code and data sets, but it could also be media, documentation, inputs to proof assistants, shell-scripts to run experiments, etc.
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Towards Pervasive and User Satisfactory CNN across GPU Microarchitectures

Mingcong Song, Yang Hu, Huixiang Chen, Tao Li

Towards Pervasive and User Satisfactory CNN across GPU Microarchitectures

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ATOM: Atomic Durability in Non-volatile Memory through Hardware Logging

Arpit Joshi, Vijay Nagarajan, Stratis Viglas, Marcelo Cintra

ATOM: Atomic Durability in Non-volatile Memory through Hardware Logging

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SWAP: Effective Fine-Grain Management of Shared Last-Level Caches with Minimum Hardware Support

Xiaodong Wang, Shuang Chen, Jeff Setter, José F. Martínez

SWAP: Effective Fine-Grain Management of Shared Last-Level Caches with Minimum Hardware Support

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Controlled Kernel Launch for Dynamic Parallelism in GPUs

Xulong Tang, Ashutosh Pattnaik, Huaipan Jiang, Onur Kayiran, Adwait Jog, Sreepathi Pai, Mohamed Ibrahim, Mahmut T. Kandemir, Chita R. Das

Controlled Kernel Launch for Dynamic Parallelism in GPUs

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Efficient Sequential Consistency in GPUs via Relativistic Cache Coherence

Xiaowei Ren, Mieszko Lis

Efficient Sequential Consistency in GPUs via Relativistic Cache Coherence

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Cold Boot Attacks are Still Hot: Security Analysis of Memory Scramblers in Modern Processors

Salessawi Ferede Yitbarek, Misiker Tadesse Aga, Reetuparna Das, Todd M. Austin

Cold Boot Attacks are Still Hot: Security Analysis of Memory Scramblers in Modern Processors

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SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures

Yuhwan Ro, Hyunyoon Cho, Eojin Lee, Daejin Jung, Young Hoon Son, Jung Ho Ahn, Jae W. Lee

SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures

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Pilot Register File: Energy Efficient Partitioned Register File for GPUs

Mohammad Abdel-Majeed, Alireza Shafaei, Hyeran Jeon, Massoud Pedram, Murali Annavaram

Pilot Register File: Energy Efficient Partitioned Register File for GPUs

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Processing-in-Memory Enabled Graphics Processors for 3D Rendering

Chenhao Xie, Shuaiwen Leon Song, Jing Wang, Weigong Zhang, Xin Fu

Processing-in-Memory Enabled Graphics Processors for 3D Rendering

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Reliability-Aware Scheduling on Heterogeneous Multicore Processors

Ajeya Naithani, Stijn Eyerman, Lieven Eeckhout

Reliability-Aware Scheduling on Heterogeneous Multicore Processors

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Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices

Sang-uhn Cha, Seongil O, Hyunsung Shin, Sangjoon Hwang, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi, Gyo-Young Jin, Young Hoon Son, Hyunyoon Cho, Jung Ho Ahn, Nam Sung Kim

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices

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Hipster: Hybrid Task Manager for Latency-Critical Cloud Workloads

Rajiv Nishtala, Paul M. Carpenter, Vinicius Petrucci, Xavier Martorell

Hipster: Hybrid Task Manager for Latency-Critical Cloud Workloads

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SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies

Hasan Hassan, Nandita Vijaykumar, Samira Manabi Khan, Saugata Ghose, Kevin K. Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, Onur Mutlu

SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies

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Supporting Address Translation for Accelerator-Centric Architectures

Yuchen Hao, Zhenman Fang, Glenn Reinman, Jason Cong

Supporting Address Translation for Accelerator-Centric Architectures

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Near-Optimal Access Partitioning for Memory Hierarchies with Multiple Heterogeneous Bandwidth Sources

Jayesh Gaur, Mainak Chaudhuri, Pradeep Ramachandran, Sreenivas Subramoney

Near-Optimal Access Partitioning for Memory Hierarchies with Multiple Heterogeneous Bandwidth Sources

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Transparent and Efficient CFI Enforcement with Intel Processor Trace

Yutao Liu, Peitao Shi, Xinran Wang, Haibo Chen, Binyu Zang, Haibing Guan

Transparent and Efficient CFI Enforcement with Intel Processor Trace

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Needle: Leveraging Program Analysis to Analyze and Extract Accelerators from Whole Programs

Snehasish Kumar, Nick Sumner, Vijayalakshmi Srinivasan, Steve Margerm, Arrvindh Shriraman

Needle: Leveraging Program Analysis to Analyze and Extract Accelerators from Whole Programs

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KAML: A Flexible, High-Performance Key-Value SSD

Yanqin Jin, Hung-Wei Tseng, Yannis Papakonstantinou, Steven Swanson

KAML: A Flexible, High-Performance Key-Value SSD

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Maximizing Cache Performance Under Uncertainty

Nathan Beckmann, Daniel Sánchez

Maximizing Cache Performance Under Uncertainty

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PABST: Proportionally Allocated Bandwidth at the Source and Target

Derek R. Hower, Harold W. Cain, Carl A. Waldspurger

PABST: Proportionally Allocated Bandwidth at the Source and Target

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Application-Specific Performance-Aware Energy Optimization on Android Mobile Devices

Karthik Rao, Jun Wang, Sudhakar Yalamanchili, Yorai Wardi, Handong Ye

Application-Specific Performance-Aware Energy Optimization on Android Mobile Devices

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A Split Cache Hierarchy for Enabling Data-Oriented Optimizations

Andreas Sembrant, Erik Hagersten, David Black-Schaffer

A Split Cache Hierarchy for Enabling Data-Oriented Optimizations

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Design and Evaluation of AWGR-Based Photonic NoC Architectures for 2.5D Integrated High Performance Computing Systems

Paolo Grani, Roberto Proietti, Venkatesh Akella, S. J. Ben Yoo

Design and Evaluation of AWGR-Based Photonic NoC Architectures for 2.5D Integrated High Performance Computing Systems

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Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links

Sebastian Werner, Javier Navaridas, Mikel Luján

Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links

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Radiation-Induced Error Criticality in Modern HPC Parallel Accelerators

Daniel Alfonso Gonçalves de Oliveira, Laércio Lima Pilla, Mauricio Hanzich, Vinicius Fratin, Fernando Fernandes, Caio B. Lunardi, José María Cela, Philippe Olivier Alexandre Navaux, Luigi Carro, Paolo Rech

Radiation-Induced Error Criticality in Modern HPC Parallel Accelerators

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MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories

Andreas Prodromou, Mitesh R. Meswani, Nuwan Jayasena, Gabriel H. Loh, Dean M. Tullsen

MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories

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Dynamic GPGPU Power Management Using Adaptive Model Predictive Control

Abhinandan Majumdar, Leonardo Piga, Indrani Paul, Joseph L. Greathouse, Wei Huang, David H. Albonesi

Dynamic GPGPU Power Management Using Adaptive Model Predictive Control

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GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks

Lifeng Nai, Ramyad Hadidi, Jaewoong Sim, Hyojong Kim, Pranith Kumar, Hyesoon Kim

GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks

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Cooper: Task Colocation with Cooperative Games

Qiuyun Llull, Songchun Fan, Seyed Majid Zahedi, Benjamin C. Lee

Cooper: Task Colocation with Cooperative Games

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Balancing Performance and Lifetime of MLC PCM by Using a Region Retention Monitor

Mingzhe Zhang, Lunkai Zhang, Lei Jiang, Zhiyong Liu, Frederic T. Chong

Balancing Performance and Lifetime of MLC PCM by Using a Region Retention Monitor

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High-Bandwidth Low-Latency Approximate Interconnection Networks

Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi

High-Bandwidth Low-Latency Approximate Interconnection Networks

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Cooperative Path-ORAM for Effective Memory Bandwidth Sharing in Server Settings

Rujia Wang, Youtao Zhang, Jun Yang

Cooperative Path-ORAM for Effective Memory Bandwidth Sharing in Server Settings

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PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning

Linghao Song, Xuehai Qian, Hai Li, Yiran Chen

PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning

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Architecting an Energy-Efficient DRAM System for GPUs

Niladrish Chatterjee, Mike O'Connor, Donghyuk Lee, Daniel R. Johnson, Stephen W. Keckler, Minsoo Rhu, William J. Dally

Architecting an Energy-Efficient DRAM System for GPUs

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Fast and Accurate Exploration of Multi-level Caches Using Hierarchical Reuse Distance

Rafael K. V. Maeda, Qiong Cai, Jiang Xu, Zhe Wang, Zhongyuan Tian

Fast and Accurate Exploration of Multi-level Caches Using Hierarchical Reuse Distance

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Static Bubble: A Framework for Deadlock-Free Irregular On-chip Topologies

Aniruddh Ramrakhyani, Tushar Krishna

Static Bubble: A Framework for Deadlock-Free Irregular On-chip Topologies

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Partial Row Activation for Low-Power DRAM System

Yebin Lee, Hyeonggyu Kim, Seokin Hong, Soontae Kim

Partial Row Activation for Low-Power DRAM System

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BRAVO: Balanced Reliability-Aware Voltage Optimization

Karthik Swaminathan, Nandhini Chandramoorthy, Chen-Yong Cher, Ramon Bertran, Alper Buyuktosunoglu, Pradip Bose

BRAVO: Balanced Reliability-Aware Voltage Optimization

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Random Folded Clos Topologies for Datacenter Networks

Cristobal Camarero, Carmen Martínez, Ramón Beivide

Random Folded Clos Topologies for Datacenter Networks

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Design and Analysis of an APU for Exascale Computing

Thiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Bradford M. Beckmann, William C. Brantley, Joseph L. Greathouse, Wei Huang, Arun Karunanithi, Onur Kayiran, Mitesh R. Meswani, Indrani Paul, Matthew Poremba, Steven Raasch, Steven K. Reinhardt, Greg Sadowski, Vilas Sridharan

Design and Analysis of an APU for Exascale Computing

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G-Scalar: Cost-Effective Generalized Scalar Execution Architecture for Power-Efficient GPUs

Zhenhong Liu, Syed Zohaib Gilani, Murali Annavaram, Nam Sung Kim

G-Scalar: Cost-Effective Generalized Scalar Execution Architecture for Power-Efficient GPUs

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NCAP: Network-Driven, Packet Context-Aware Power Management for Client-Server Architecture

Mohammad Alian, Ahmed H. M. O. Abulila, Lokesh Jindal, Daehoon Kim, Nam Sung Kim

NCAP: Network-Driven, Packet Context-Aware Power Management for Client-Server Architecture

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Understanding and Optimizing Power Consumption in Memory Networks

Xun Jian, Pavan Kumar Hanumolu, Rakesh Kumar

Understanding and Optimizing Power Consumption in Memory Networks

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Near-Ideal Networks-on-Chip for Servers

Pejman Lotfi-Kamran, Mehdi Modarressi, Hamid Sarbazi-Azad

Near-Ideal Networks-on-Chip for Servers

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Enabling Effective Module-Oblivious Power Gating for Embedded Processors

Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori

Enabling Effective Module-Oblivious Power Gating for Embedded Processors

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Camouflage: Memory Traffic Shaping to Mitigate Timing Attacks

Yanqi Zhou, Sameer Wagh, Prateek Mittal, David Wentzlaff

Camouflage: Memory Traffic Shaping to Mitigate Timing Attacks

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Compute Caches

Shaizeen Aga, Supreet Jeloka, Arun Subramaniyan, Satish Narayanasamy, David Blaauw, Reetuparna Das

Compute Caches

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SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization

Jee Ho Ryoo, Mitesh R. Meswani, Andreas Prodromou, Lizy K. John

SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization

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Tiny Directory: Efficient Shared Memory in Many-Core Systems with Ultra-Low-Overhead Coherence Tracking

Sudhanshu Shukla, Mainak Chaudhuri

Tiny Directory: Efficient Shared Memory in Many-Core Systems with Ultra-Low-Overhead Coherence Tracking

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Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques

Yu Cai, Saugata Ghose, Yixin Luo, Ken Mai, Onur Mutlu, Erich F. Haratsch

Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques

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FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks

Wenyan Lu, Guihai Yan, Jiajun Li, Shijun Gong, Yinhe Han, Xiaowei Li

FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks

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Secure Dynamic Memory Scheduling Against Timing Channel Attacks

Yao Wang, Benjamin Wu, G. Edward Suh

Secure Dynamic Memory Scheduling Against Timing Channel Attacks

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Exploring Hyperdimensional Associative Memory

Mohsen Imani, Abbas Rahimi, Deqian Kong, Tajana Rosing, Jan M. Rabaey

Exploring Hyperdimensional Associative Memory

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Boomerang: A Metadata-Free Architecture for Control Flow Delivery

Rakesh Kumar, Cheng-Chieh Huang, Boris Grot, Vijay Nagarajan

Boomerang: A Metadata-Free Architecture for Control Flow Delivery

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Fast Decentralized Power Capping for Server Clusters

Reza Azimi, Masoud Badiei, Xin Zhan, Na Li, Sherief Reda

Fast Decentralized Power Capping for Server Clusters

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