Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices

Article Details
Title:	Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices
Article URLs:	https://doi.org/10.1109/HPCA.2017.30 http://doi.ieeecomputersociety.org/10.1109/HPCA.2017.30
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Authors:	Sang-uhn Cha	Samsung Electronics
	Seongil O	Samsung Electronics
	Hyunsung Shin	Samsung Electronics
	Sangjoon Hwang	Samsung Electronics
	Kwang-Il Park	Samsung Electronics
	Seong-Jin Jang	Samsung Electronics
	Joo-Sun Choi	Samsung Electronics
	Gyo-Young Jin	Samsung Electronics
	Young Hoon Son	Samsung Electronics
	Hyunyoon Cho	Samsung Electronics Seoul National University
	Jung Ho Ahn	Seoul National University
	Nam Sung Kim	University of Illinois Urbana-Champaign
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DBLP Key:	conf/hpca/ChaOSHPJCJSCAK17
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IEEE International Symposium on High Performance Computer Architecture, HPCA 2017