IEEE Real-Time Systems Symposium, RTSS 2018


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Title: Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core
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Authors: Sebastian Hahn
  • Saarland University, Saarland Informatics Campus
Jan Reineke
  • Saarland University, Saarland Informatics Campus
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DBLP Key: conf/rtss/0001R18
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