Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity

Article Details
Title:	Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity
Article URLs:	https://doi.org/10.1109/ISLPED.2017.8009189
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Authors:	Bon Woong Ku	Georgia Institute of Technology, School of ECE
	Taigon Song	Synopsys Inc.
	Arthur Nieuwoudt	Synopsys Inc.
	Sung Kyu Lim	Georgia Institute of Technology, School of ECE
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DBLP Key:	conf/islped/KuSNL17
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IEEE/ACM Intl. Symposium on Low Power Electronics and Design, ISLPED 2017