Integrating 3D Resistive Memory Cache into GPGPU for Energy-Efficient Data Processing

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Title:	Integrating 3D Resistive Memory Cache into GPGPU for Energy-Efficient Data Processing
Article URLs:	https://doi.org/10.1109/PACT.2015.60 http://doi.ieeecomputersociety.org/10.1109/PACT.2015.60
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Authors:	Jie Zhang	Yonsei University, School of Integrated Technology Yonsei University, Yonsei Institute Convergence Technology
	David Donofrio	Lawrence Berkeley National Laboratory, Computer Architecture Laboratory
	John Shalf	Lawrence Berkeley National Laboratory, Computer Architecture Laboratory
	Myoungsoo Jung	Yonsei University, School of Integrated Technology Yonsei University, Yonsei Institute Convergence Technology
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DBLP Key:	conf/IEEEpact/ZhangDSJ15
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IEEE/ACM Intl. Conf. on Parallel Architectures and Compilation Techniques, PACT 2015