| Title/Authors | Title | Research Artifacts
[?] A research
artifact is any by-product of a research project that is not
directly included in the published research paper. In Computer
Science research this is often source code and data sets, but
it could also be media, documentation, inputs to proof
assistants, shell-scripts to run experiments, etc.
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Shin-Ying Lee, Akhil Arunkumar, Carole-Jean Wu |
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Manycore network interfaces for in-memory rack-scale computing Alexandros Daglis, Stanko Novakovic, Edouard Bugnion, Babak Falsafi, Boris Grot |
Manycore network interfaces for in-memory rack-scale computing Details |
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The load slice core microarchitecture Trevor E. Carlson, Wim Heirman, Osman Allam, Stefanos Kaxiras, Lieven Eeckhout |
The load slice core microarchitecture Details |
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SLIP: reducing wire energy in the memory hierarchy Subhasis Das, Tor M. Aamodt, William J. Dally |
SLIP: reducing wire energy in the memory hierarchy Details |
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ShiDianNao: shifting vision processing closer to the sensor Zidong Du, Robert Fasthuber, Tianshi Chen, Paolo Ienne, Ling Li, Tao Luo, Xiaobing Feng, Yunji Chen, Olivier Temam |
ShiDianNao: shifting vision processing closer to the sensor Details |
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Accelerating asynchronous programs through event sneak peek Gaurav Chadha, Scott A. Mahlke, Satish Narayanasamy |
Accelerating asynchronous programs through event sneak peek Details |
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FaultHound: value-locality-based soft-fault tolerance Nitin, Irith Pomeranz, T. N. Vijaykumar |
FaultHound: value-locality-based soft-fault tolerance Details |
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Tianwei Zhang, Ruby B. Lee |
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Rumba: an online quality management system for approximate computing Daya Shanker Khudia, Babak Zamirai, Mehrzad Samadi, Scott A. Mahlke |
Rumba: an online quality management system for approximate computing Details |
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Semantic locality and context-based prefetching using reinforcement learning Leeor Peled, Shie Mannor, Uri C. Weiser, Yoav Etsion |
Semantic locality and context-based prefetching using reinforcement learning Details |
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Page overlays: an enhanced virtual memory framework to enable fine-grained memory management Vivek Seshadri, Gennady Pekhimenko, Olatunji Ruwase, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry, Trishul M. Chilimbi |
Page overlays: an enhanced virtual memory framework to enable fine-grained memory management Details |
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Exploring the potential of heterogeneous von neumann/dataflow execution models Tony Nowatzki, Vinay Gangadhar, Karthikeyan Sankaralingam |
Exploring the potential of heterogeneous von neumann/dataflow execution models Details |
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ArMOR: defending against memory consistency model mismatches in heterogeneous architectures Daniel Lustig, Caroline Trippel, Michael Pellauer, Margaret Martonosi |
ArMOR: defending against memory consistency model mismatches in heterogeneous architectures Details |
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Cost-effective speculative scheduling in high performance processors Arthur Perais, André Seznec, Pierre Michaud, Andreas Sembrant, Erik Hagersten |
Cost-effective speculative scheduling in high performance processors Details |
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COP: to compress and protect main memory David J. Palframan, Nam Sung Kim, Mikko H. Lipasti |
COP: to compress and protect main memory Details |
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Efficient execution of memory access phases using dataflow specialization Chen-Han Ho, Sung Jin Kim, Karthikeyan Sankaralingam |
Efficient execution of memory access phases using dataflow specialization Details |
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VIP: virtualizing IP chains on handheld platforms Nachiappan Chidambaram Nachiappan, Haibo Zhang, Jihyun Ryoo, Niranjan Soundararajan, Anand Sivasubramaniam, Mahmut T. Kandemir, Ravishankar R. Iyer, Chita R. Das |
VIP: virtualizing IP chains on handheld platforms Details |
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Heracles: improving resource efficiency at scale David Lo, Liqun Cheng, Rama Govindaraju, Parthasarathy Ranganathan, Christos Kozyrakis |
Heracles: improving resource efficiency at scale Details |
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Profiling a warehouse-scale computer Svilen Kanev, Juan Pablo Darago, Kim M. Hazelwood, Parthasarathy Ranganathan, Tipp Moseley, Gu-Yeon Wei, David M. Brooks |
Profiling a warehouse-scale computer Details |
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Characterization paper, no artefacts. We will eventually release traces/benchmarks representative of the systems characterized here.
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Research produced no artifacts
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Redundant memory mappings for fast access to large memories Vasileios Karakostas, Jayneel Gandhi, Furkan Ayar, Adrián Cristal, Mark D. Hill, Kathryn S. McKinley, Mario Nemirovsky, Michael M. Swift, Osman S. Unsal |
Redundant memory mappings for fast access to large memories Details |
Author Comments:
The tool was used to derive the results of the paper.
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MBus: an ultra-low power interconnect bus for next generation nanopower systems Pat Pannuto, Yoonmyung Lee, Ye-Sheng Kuo, Zhiyoong Foo, Benjamin P. Kempke, Gyouho Kim, Ronald G. Dreslinski, David T. Blaauw, Prabal Dutta |
MBus: an ultra-low power interconnect bus for next generation nanopower systems Details |
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FASE: finding amplitude-modulated side-channel emanations Robert Locke Callan, Alenka G. Zajic, Milos Prvulovic |
FASE: finding amplitude-modulated side-channel emanations Details |
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Jin Wang, Norm Rubin, Albert Sidelnik, Sudhakar Yalamanchili |
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Harmonia: balancing compute and memory power in high-performance GPUs Indrani Paul, Wei Huang, Manish Arora, Sudhakar Yalamanchili |
Harmonia: balancing compute and memory power in high-performance GPUs Details |
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Nandita Vijaykumar, Gennady Pekhimenko, Adwait Jog, Abhishek Bhowmick, Rachata Ausavarungnirun, Chita R. Das, Mahmut T. Kandemir, Todd C. Mowry, Onur Mutlu |
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DjiNN and Tonic: DNN as a service and its implications for future warehouse scale computers Johann Hauswald, Yiping Kang, Michael A. Laurenzano, Quan Chen, Cheng Li, Trevor N. Mudge, Ronald G. Dreslinski, Jason Mars, Lingjia Tang |
DjiNN and Tonic: DNN as a service and its implications for future warehouse scale computers Details |
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Computer performance microscopy with Shim Xi Yang, Stephen M. Blackburn, Kathryn S. McKinley |
Computer performance microscopy with Shim Details |
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Sheng Li, Hyeontaek Lim, Victor W. Lee, Jung Ho Ahn, Anuj Kalia, Michael Kaminsky, David G. Andersen, Seongil O, Sukhan Lee, Pradeep Dubey |
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BlueDBM: an appliance for big data analytics Sang Woo Jun, Ming Liu, Sungjin Lee, Jamey Hicks, John Ankcorn, Myron King, Shuotao Xu, Arvind |
BlueDBM: an appliance for big data analytics Details |
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A fully associative, tagless DRAM cache Yongjun Lee, Jongwon Kim, Hakbeom Jang, Hyunggyun Yang, Jangwoo Kim, Jinkyu Jeong, Jae W. Lee |
A fully associative, tagless DRAM cache Details |
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Stash: have your scratchpad and cache it too Rakesh Komuravelli, Matthew D. Sinclair, Johnathan Alsop, Muhammad Huzaifa, Maria Kotsifakou, Prakalp Srivastava, Sarita V. Adve, Vikram S. Adve |
Stash: have your scratchpad and cache it too Details |
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Matt Skach, Manish Arora, Chang-Hong Hsu, Qi Li, Dean M. Tullsen, Lingjia Tang, Jason Mars |
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Data reorganization in memory using 3D-stacked DRAM Berkin Akin, Franz Franchetti, James C. Hoe |
Data reorganization in memory using 3D-stacked DRAM Details |
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Branch vanguard: decomposing branch functionality into prediction and resolution instructions Daniel S. McFarlin, Craig B. Zilles |
Branch vanguard: decomposing branch functionality into prediction and resolution instructions Details |
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DynaSpAM: dynamic spatial architecture mapping using out of order instruction schedules Feng Liu, Heejin Ahn, Stephen R. Beard, Taewook Oh, David I. August |
DynaSpAM: dynamic spatial architecture mapping using out of order instruction schedules Details |
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Görkem Asilioglu, Zhaoxiang Jin, Murat Köksal, Omkar Javeri, Soner Önder |
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Reducing world switches in virtualized environment with flexible cross-world calls Wenhao Li, Yubin Xia, Haibo Chen, Binyu Zang, Haibing Guan |
Reducing world switches in virtualized environment with flexible cross-world calls Details |
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Clean: a race detector with cleaner semantics Cedomir Segulja, Tarek S. Abdelrahman |
Clean: a race detector with cleaner semantics Details |
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PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi |
PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture Details |
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Not able to share produced artifacts
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Lluc Alvarez, Lluís Vilanova, Miquel Moretó, Marc Casas, Marc González, Xavier Martorell, Nacho Navarro, Eduard Ayguadé, Mateo Valero |
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PrORAM: dynamic prefetcher for oblivious RAM Xiangyao Yu, Syed Kamran Haider, Ling Ren, Christopher W. Fletcher, Albert Kwon, Marten van Dijk, Srinivas Devadas |
PrORAM: dynamic prefetcher for oblivious RAM Details |
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HEB: deploying and managing hybrid energy buffers for improving datacenter efficiency and economy Longjun Liu, Chao Li, Hongbin Sun, Yang Hu, Juncheng Gu, Tao Li, Jingmin Xin, Nanning Zheng |
HEB: deploying and managing hybrid energy buffers for improving datacenter efficiency and economy Details |
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Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions Ishwar Bhati, Zeshan Chishti, Shih-Lien Lu, Bruce Jacob |
Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions Details |
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Multiple clone row DRAM: a low latency and area optimized DRAM Jungwhan Choi, Wongyu Shin, Jaemin Jang, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Lee-Sup Kim |
Multiple clone row DRAM: a low latency and area optimized DRAM Details |
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BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi |
BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches Details |
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A variable warp size architecture Timothy G. Rogers, Daniel R. Johnson, Mike O'Connor, Stephen W. Keckler |
A variable warp size architecture Details |
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Towards sustainable in-situ server systems in the big data era Chao Li, Yang Hu, Longjun Liu, Juncheng Gu, Mingcong Song, Xiaoyao Liang, Jingling Yuan, Tao Li |
Towards sustainable in-situ server systems in the big data era Details |
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SHRINK: reducing the ISA complexity via instruction recycling Bruno Cardoso Lopes, Rafael Auler, Luiz Ramos, Edson Borin, Rodolfo Azevedo |
SHRINK: reducing the ISA complexity via instruction recycling Details |
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Probable cause: the deanonymizing effects of approximate DRAM Amir Rahmati, Matthew Hicks, Daniel E. Holcomb, Kevin Fu |
Probable cause: the deanonymizing effects of approximate DRAM Details |
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Flexible software profiling of GPU architectures Mark Stephenson, Siva Kumar Sastry Hari, Yunsup Lee, Eiman Ebrahimi, Daniel R. Johnson, David W. Nellans, Mike O'Connor, Stephen W. Keckler |
Flexible software profiling of GPU architectures Details |
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Warped-compression: enabling power efficient GPUs through register compression Sangpil Lee, Keunsoo Kim, Gunjae Koo, Hyeran Jeon, Won Woo Ro, Murali Annavaram |
Warped-compression: enabling power efficient GPUs through register compression Details |
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Hi-fi playback: tolerating position errors in shift operations of racetrack memory Chao Zhang, Guangyu Sun, Xian Zhang, Weiqi Zhang, Weisheng Zhao, Tao Wang, Yun Liang, Yongpan Liu, Yu Wang, Jiwu Shu |
Hi-fi playback: tolerating position errors in shift operations of racetrack memory Details |
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A scalable processing-in-memory accelerator for parallel graph processing Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, Kiyoung Choi |
A scalable processing-in-memory accelerator for parallel graph processing Details |
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Not able to share produced artifacts
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Callback: efficient synchronization without invalidation with a directory just for spin-waiting Alberto Ros, Stefanos Kaxiras |
Callback: efficient synchronization without invalidation with a directory just for spin-waiting Details |
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Takuya Nakaike, Rei Odaira, Matthew Gaudet, Maged M. Michael, Hisanobu Tomari |
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Unified address translation for memory-mapped SSDs with FlashMap Jian Huang, Anirudh Badam, Moinuddin K. Qureshi, Karsten Schwan |
Unified address translation for memory-mapped SSDs with FlashMap Details |
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Fusion: design tradeoffs in coherent cache hierarchies for accelerators Snehasish Kumar, Arrvindh Shriraman, Naveen Vedula |
Fusion: design tradeoffs in coherent cache hierarchies for accelerators Details |
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MiSAR: minimalistic synchronization accelerator with resource overflow management Ching-Kai Liang, Milos Prvulovic |
MiSAR: minimalistic synchronization accelerator with resource overflow management Details |
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