| Title/Authors | Title | Research Artifacts
[?] A research
artifact is any by-product of a research project that is not
directly included in the published research paper. In Computer
Science research this is often source code and data sets, but
it could also be media, documentation, inputs to proof
assistants, shell-scripts to run experiments, etc.
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ATCache: reducing DRAM cache latency via a small SRAM tag cache Cheng-Chieh Huang, Vijay Nagarajan |
ATCache: reducing DRAM cache latency via a small SRAM tag cache Details |
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A runtime support mechanism for fast mode switching of a self-morphing core for power efficiency Sudarshan Srinivasan, Nithesh kurella, Israel Koren, Rance Rodrigues, Sandip Kundu |
A runtime support mechanism for fast mode switching of a self-morphing core for power efficiency Details |
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XStream: cross-core spatial streaming based MLC prefetchers for parallel applications in CMPs Biswabandan Panda, Shankar Balachandran |
XStream: cross-core spatial streaming based MLC prefetchers for parallel applications in CMPs Details |
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Consolidated conflict detection for hardware transactional memory Lihang Zhao, Jeffrey T. Draper |
Consolidated conflict detection for hardware transactional memory Details |
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Domain-specific models for innovation in analytics Bob Blainey |
Domain-specific models for innovation in analytics Details |
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Kishore Kumar Pusukuri, Rajiv Gupta, Laxmi N. Bhuyan |
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Sreepathi Pai, R. Govindarajan, Matthew J. Thazhuthaveetil |
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Design for scalability in enterprise SSDs Arash Tavakkol, Mohammad Arjomand, Hamid Sarbazi-Azad |
Design for scalability in enterprise SSDs Details |
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CAWS: criticality-aware warp scheduling for GPGPU workloads Shin-Ying Lee, Carole-Jean Wu |
CAWS: criticality-aware warp scheduling for GPGPU workloads Details |
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Locality-aware memory association for multi-target worksharing in OpenMP Thomas R. W. Scogland, Wu-Chun Feng |
Locality-aware memory association for multi-target worksharing in OpenMP Details |
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Memory scheduling towards high-throughput cooperative heterogeneous computing Hao Wang, Ripudaman Singh, Michael J. Schulte, Nam Sung Kim |
Memory scheduling towards high-throughput cooperative heterogeneous computing Details |
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An event-based language for dynamic binary translation frameworks Serguei Makarov, Angela Demke Brown, Ashvin Goel |
An event-based language for dynamic binary translation frameworks Details |
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Rollback-free value prediction with approximate loads Bradley Thwaites, Gennady Pekhimenko, Hadi Esmaeilzadeh, Amir Yazdanbakhsh, Onur Mutlu, Jongse Park, Girish Mururu, Todd C. Mowry |
Rollback-free value prediction with approximate loads Details |
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PEMOGEN: automatic adaptive performance modeling during program runtime Arnamoy Bhattacharyya, Torsten Hoefler |
PEMOGEN: automatic adaptive performance modeling during program runtime Details |
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Velociraptor: an embedded compiler toolkit for numerical programs targeting CPUs and GPUs Rahul Garg, Laurie J. Hendren |
Velociraptor: an embedded compiler toolkit for numerical programs targeting CPUs and GPUs Details |
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Optimizing stencil code via locality of computation Yulong Luo, Guangming Tan |
Optimizing stencil code via locality of computation Details |
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PATS: pattern aware scheduling and power gating for GPGPUs Qiumin Xu, Murali Annavaram |
PATS: pattern aware scheduling and power gating for GPGPUs Details |
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D2MA: accelerating coarse-grained data transfer for GPUs Davoud Anoushe Jamshidi, Mehrzad Samadi, Scott A. Mahlke |
D2MA: accelerating coarse-grained data transfer for GPUs Details |
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LCA: a memory link and cache-aware co-scheduling approach for CMPs Alexandros-Herodotos Haritatos, Georgios I. Goumas, Nikos Anastopoulos, Konstantinos Nikas, Kornilios Kourtis, Nectarios Koziris |
LCA: a memory link and cache-aware co-scheduling approach for CMPs Details |
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Using STT-RAM to enable energy-efficient near-threshold chip multiprocessors Xiang Pan, Radu Teodorescu |
Using STT-RAM to enable energy-efficient near-threshold chip multiprocessors Details |
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A run-time power manager exploiting software parallelism Simon Holmbacka, Sébastien Lafond, Johan Lilius |
A run-time power manager exploiting software parallelism Details |
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SpongeDirectory: flexible sparse directories utilizing multi-level memristors Lunkai Zhang, Dmitri B. Strukov, Hebatallah Saadeldeen, Dongrui Fan, Mingzhe Zhang, Diana Franklin |
SpongeDirectory: flexible sparse directories utilizing multi-level memristors Details |
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ArrayTool: a lightweight profiler to guide array regrouping Xu Liu, Kamal Sharma, John M. Mellor-Crummey |
ArrayTool: a lightweight profiler to guide array regrouping Details |
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ADHA: automatic data layout framework for heterogeneous architectures Deepak Majeti, Kuldeep S. Meel, Rajkishore Barik, Vivek Sarkar |
ADHA: automatic data layout framework for heterogeneous architectures Details |
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Improving performance of streaming applications with filtering and control messages Peng Li, Jeremy Buhler |
Improving performance of streaming applications with filtering and control messages Details |
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Graph-based performance accounting for chip multiprocessor memory systems Magnus Jahre |
Graph-based performance accounting for chip multiprocessor memory systems Details |
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Alessandro Fanfarillo, Tobias Burnus, Valeria Cardellini, Salvatore Filippone, Dan Nagle, Damian W. I. Rouson |
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Data-reuse optimizations for pipelined tiling with parametric tile sizes Alexandre Isoard |
Data-reuse optimizations for pipelined tiling with parametric tile sizes Details |
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RCS: runtime resource and core scaling for power-constrained multi-core processors Hamid Reza Ghasemi, Nam Sung Kim |
RCS: runtime resource and core scaling for power-constrained multi-core processors Details |
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What is the cost of weak determinism? Cedomir Segulja, Tarek S. Abdelrahman |
What is the cost of weak determinism? Details |
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Protection and utilization in shared cache through rationing Raj Parihar, Jacob Brock, Chen Ding, Michael C. Huang |
Protection and utilization in shared cache through rationing Details |
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Tiling and optimizing time-iterated computations on periodic domains Uday Bondhugula, Vinayaka Bandishti, Albert Cohen, Guillain Potron, Nicolas Vasilache |
Tiling and optimizing time-iterated computations on periodic domains Details |
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Versatile and scalable parallel histogram construction Wookeun Jung, Jongsoo Park, Jaejin Lee |
Versatile and scalable parallel histogram construction Details |
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KLA: a new algorithmic paradigm for parallel graph computations Harshvardhan, Adam Fidel, Nancy M. Amato, Lawrence Rauchwerger |
KLA: a new algorithmic paradigm for parallel graph computations Details |
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Bounded memory scheduling of dynamic task graphs Dragos Sbirlea, Zoran Budimlic, Vivek Sarkar |
Bounded memory scheduling of dynamic task graphs Details |
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Virtues and limitations of commodity hardware transactional memory Nuno Diegues, Paolo Romano, Luís E. T. Rodrigues |
Virtues and limitations of commodity hardware transactional memory Details |
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COLORIS: a dynamic cache partitioning system using page coloring Ying Ye, Richard West, Zhuoqun Cheng, Ye Li |
COLORIS: a dynamic cache partitioning system using page coloring Details |
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ILP and TLP in shared memory applications: a limit study Ehsan Fatehi, Paul Gratz |
ILP and TLP in shared memory applications: a limit study Details |
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The research artifacts from this paper unfortunately have been lost in the intervening years since publication.
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Jennifer B. Sartor, Wim Heirman, Stephen M. Blackburn, Lieven Eeckhout, Kathryn S. McKinley |
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Active learning accelerated automatic heuristic construction for parallel program mapping William F. Ogilvie, Pavlos Petoumenos, Zheng Wang, Hugh Leather |
Active learning accelerated automatic heuristic construction for parallel program mapping Details |
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From petascale to the pocket: Adaptively scaling parallel programs for mobile SoCs Adam Fidel, Nancy M. Amato, Lawrence Rauchwerger |
From petascale to the pocket: Adaptively scaling parallel programs for mobile SoCs Details |
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SQRL: hardware accelerator for collecting software data structures Snehasish Kumar, Arrvindh Shriraman, Vijayalakshmi Srinivasan, Dan Lin, Jordon Phillips |
SQRL: hardware accelerator for collecting software data structures Details |
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SM-centric transformation: circumventing hardware restrictions for flexible GPU scheduling Bo Wu, Guoyang Chen, Dong Li, Xipeng Shen, Jeffrey S. Vetter |
SM-centric transformation: circumventing hardware restrictions for flexible GPU scheduling Details |
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DeSTM: harnessing determinism in STMs for application development Kaushik Ravichandran, Ada Gavrilovska, Santosh Pande |
DeSTM: harnessing determinism in STMs for application development Details |
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Processing big data graphs on memory-restricted systems Harshvardhan, Nancy M. Amato, Lawrence Rauchwerger |
Processing big data graphs on memory-restricted systems Details |
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Automatic optimization of thread-coarsening for graphics processors Alberto Magni, Christophe Dubach, Michael F. P. O'Boyle |
Automatic optimization of thread-coarsening for graphics processors Details |
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Stratified sampling for even workload partitioning Jeeva Paudel, José Nelson Amaral |
Stratified sampling for even workload partitioning Details |
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Automatic execution of single-GPU computations across multiple GPUs Javier Cabezas, Lluís Vilanova, Isaac Gelado, Thomas B. Jablin, Nacho Navarro, Wen-mei W. Hwu |
Automatic execution of single-GPU computations across multiple GPUs Details |
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Compiler support for selective page migration in NUMA architectures Guilherme Piccoli, Henrique Nazaré Santos, Raphael Ernani Rodrigues, Christiane Pousa, Edson Borin, Fernando Magno Quintão Pereira |
Compiler support for selective page migration in NUMA architectures Details |
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kMAF: automatic kernel-level management of thread and data affinity Matthias Diener, Eduardo Henrique Molina da Cruz, Philippe Olivier Alexandre Navaux, Anselm Busse, Hans-Ulrich Heiß |
kMAF: automatic kernel-level management of thread and data affinity Details |
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Bitwise data parallelism in regular expression matching Robert D. Cameron, Thomas C. Shermer, Arrvindh Shriraman, Kenneth S. Herdy, Dan Lin, Benjamin R. Hull, Meng Lin |
Bitwise data parallelism in regular expression matching Details |
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Adaptive heterogeneous scheduling for integrated GPUs Rashid Kaleem, Rajkishore Barik, Tatiana Shpeisman, Brian T. Lewis, Chunling Hu, Keshav Pingali |
Adaptive heterogeneous scheduling for integrated GPUs Details |
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Measuring flexibility in single-ISA heterogeneous processors Erik Tomusk, Christophe Dubach, Michael F. P. O'Boyle |
Measuring flexibility in single-ISA heterogeneous processors Details |
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Internet of mobile things: challenges and opportunities Klara Nahrstedt |
Internet of mobile things: challenges and opportunities Details |
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Heterogeneous microarchitectures trump voltage scaling for low-power cores Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Ronald G. Dreslinski, Thomas F. Wenisch, Scott A. Mahlke |
Heterogeneous microarchitectures trump voltage scaling for low-power cores Details |
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Design of a hybrid MPI-CUDA benchmark suite for CPU-GPU clusters Tejaswi Agarwal, Michela Becchi |
Design of a hybrid MPI-CUDA benchmark suite for CPU-GPU clusters Details |
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EFetch: optimizing instruction fetch for event-driven webapplications Gaurav Chadha, Scott A. Mahlke, Satish Narayanasamy |
EFetch: optimizing instruction fetch for event-driven webapplications Details |
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OpenTuner: an extensible framework for program autotuning Jason Ansel, Shoaib Kamil, Kalyan Veeramachaneni, Jonathan Ragan-Kelley, Jeffrey Bosboom, Una-May O'Reilly, Saman P. Amarasinghe |
OpenTuner: an extensible framework for program autotuning Details |
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Automatic parallelism through macro dataflow in high-level array languages Pushkar Ratnalikar, Arun Chauhan |
Automatic parallelism through macro dataflow in high-level array languages Details |
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Invyswell: a hybrid transactional memory for haswell's restricted transactional memory Irina Calciu, Justin Gottschlich, Tatiana Shpeisman, Gilles Pokam, Maurice Herlihy |
Invyswell: a hybrid transactional memory for haswell's restricted transactional memory Details |
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VAST: the illusion of a large memory space for GPUs Janghaeng Lee, Mehrzad Samadi, Scott A. Mahlke |
VAST: the illusion of a large memory space for GPUs Details |
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Realm: an event-based low-level runtime for distributed memory architectures Sean Treichler, Michael Bauer, Alex Aiken |
Realm: an event-based low-level runtime for distributed memory architectures Details |
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Data remapping for an energy efficient burst chop in DRAM memory systems Sudharsan Jagathrakshakan, Venkata Kalyan Tavva, Madhu Mutyam |
Data remapping for an energy efficient burst chop in DRAM memory systems Details |
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Trading cache hit rate for memory performance Wei Ding, Mahmut T. Kandemir, Diana Guttman, Adwait Jog, Chita R. Das, Praveen Yedlapalli |
Trading cache hit rate for memory performance Details |
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Warp-aware trace scheduling for GPUs James A. Jablin, Thomas B. Jablin, Onur Mutlu, Maurice Herlihy |
Warp-aware trace scheduling for GPUs Details |
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