| Title: |
Coherence Stalls or Latency Tolerance: Informed CPU Scheduling for Socket and Core Sharing |
| Article URLs: |
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| Alternative Article URLs: |
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| Authors: |
Sharanyan Srikanthan |
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University of Rochester, Department of Computer Science
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| Sandhya Dwarkadas |
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University of Rochester, Department of Computer Science
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| Kai Shen |
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University of Rochester, Department of Computer Science
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| Sharing: |
Unknown
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| Verification: |
Authors have
not verified
information
|
| Artifact Evaluation Badge: |
none
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| Artifact URLs: |
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| Artifact Correspondence Email Addresses: |
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| NSF Award Numbers: |
1217372,
1217920,
1239423,
1255729,
1319353,
1319417,
137224
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| DBLP Key: |
conf/usenix/SrikanthanDS16
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| Author Comments: |
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