ACM Conference on Embedded Network Sensor Systems, SenSys 2015


Article Details
Title: Bolt: A Stateful Processor Interconnect
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Authors: Felix Sutton
  • ETH Zurich, Switzerland, Computer Engineering and Networks Laboratory
Marco Zimmerling
  • ETH Zurich, Switzerland, Computer Engineering and Networks Laboratory
Reto Da Forno
  • ETH Zurich, Switzerland, Computer Engineering and Networks Laboratory
Roman Lim
  • ETH Zurich, Switzerland, Computer Engineering and Networks Laboratory
Tonio Gsell
  • ETH Zurich, Switzerland, Computer Engineering and Networks Laboratory
Georgia Giannopoulou
  • ETH Zurich, Switzerland, Computer Engineering and Networks Laboratory
Federico Ferrari
  • ETH Zurich, Switzerland, Computer Engineering and Networks Laboratory
Jan Beutel
  • ETH Zurich, Switzerland, Computer Engineering and Networks Laboratory
Lothar Thiele
  • ETH Zurich, Switzerland, Computer Engineering and Networks Laboratory
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DBLP Key: conf/sensys/SuttonZFLGGFBT15
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