ECC Parity: A Technique for Efficient Memory Error Resilience for Multi-Channel Memory Systems

Article Details
Title:	ECC Parity: A Technique for Efficient Memory Error Resilience for Multi-Channel Memory Systems
Article URLs:	https://doi.org/10.1109/SC.2014.89 http://doi.ieeecomputersociety.org/10.1109/SC.2014.89
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Authors:	Xun Jian	University of Illinois at Urbana-Champaign
Authors:	Rakesh Kumar	University of Illinois at Urbana-Champaign
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DBLP Key:	conf/sc/Jian014
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ACM/IEEE Intl. Conf. for High Perf. Computing, Networking, Storage and Analysis, SC 2014