IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2016


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Title: Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems
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Authors: David Trilla
  • Barcelona Supercomputing Center
  • Universitat Politècnica de Catalunya
Javier Jalle
  • Barcelona Supercomputing Center
  • Universitat Politècnica de Catalunya
Mikel Fernández
  • Barcelona Supercomputing Center
Jaume Abella
  • Barcelona Supercomputing Center
Francisco J. Cazorla
  • Spanish National Research Council
  • Barcelona Supercomputing Center
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DBLP Key: conf/rtas/TrillaJFAC16
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