| Title: |
IEEE 802.1Qbv Gate Control List Synthesis Using Array Theory Encoding |
| Article URLs: |
|
| Alternative Article URLs: |
|
| Authors: |
Ramon Serna Oliver |
-
TTTech Computertechnik AG, Vienna
|
| Silviu S. Craciunas |
-
TTTech Computertechnik AG, Vienna
|
| Wilfried Steiner |
-
TTTech Computertechnik AG, Vienna
|
| Sharing: |
Unknown
|
| Verification: |
Authors have
not verified
information
|
| Artifact Evaluation Badge: |
none
|
| Artifact URLs: |
|
| Artifact Correspondence Email Addresses: |
|
| NSF Award Numbers: |
|
| DBLP Key: |
conf/rtas/OliverCS18
|
| Author Comments: |
|