Modular Deductive Verification of Multiprocessor Hardware Designs

Article Details
Title:	Modular Deductive Verification of Multiprocessor Hardware Designs
Article URLs:	https://doi.org/10.1007/978-3-319-21668-3_7
Alternative Article URLs:
Authors:	Muralidaran Vijayaraghavan	MIT
	Adam Chlipala	MIT
	Arvind	MIT
	Nirav Dave	SRI International
Sharing:	Research produced artifacts
Verification:	Authors have verified information
Artifact Evaluation Badge:	none
Artifact URLs:	https://github.com/vmurali/SeqConsistency
Artifact Correspondence Email Addresses:	vmurali@csail.mit.edu
NSF Award Numbers:	1253229
DBLP Key:	conf/cav/VijayaraghavanC15
Author Comments:

Computer Aided Verification, CAV 2015